2014 Fiscal Year Final Research Report
A new class of expressions for reversible logic synthesis and its minimization algorithm
| Project/Area Number |
24500053
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Iwate University |
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Principal Investigator |
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| Research Collaborator |
MURAYAMA Tatsuro
ALI Md Belayet
SUGAWARA Hayato
MATSUO Wataru
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| Project Period (FY) |
2012-04-01 – 2015-03-31
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| Keywords | 可逆論理回路 / AND-EXOR論理式 |
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| Outline of Final Research Achievements |
The reversible logic synthesis with as fewer quantum gates as possible is required to implement quantum computers. The novelty of this research is that a new class of AND-EXOR expressions, AESPs, is proposed in order to synthesize reversible circuits. Consequently, the minimization problem of gates in reversible circuits has been reduced to the minimization of products in AESPs. Moreover, minimization algorithms for AESPs and lower bounds on the gate count of reversible circuits have been presented. These results contributes to the synthesis of quantum circuits and possibly to the implementation of future quantum computers.
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| Free Research Field |
情報工学
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