Theory and Design of Post-Silicon Multi-Way Tuning for New Generation LSI Circuits

2017 Fiscal Year Final Research Report

• Project/Area Number: 26420303
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Japan Advanced Institute of Science and Technology
• Principal Investigator: Kaneko Mineo 北陸先端科学技術大学院大学, 先端科学技術研究科, 教授 (00185935)
• Research Collaborator: ZHANG Renyuan ; OH Junghoon ; KATSUMATA Kazuho ; SOGA Makoto ; SHIMURA Kai
• Project Period (FY): 2014-04-01 – 2018-03-31
• Keywords: クロック周波数 / クロックスキュー / 基盤バイアス / セットアップ条件・ホールド条件 / 高位合成 / 資源割り当て / 最適化

Outline of Final Research Achievements

Timing failure and performance degradation due to process variations are serious problems for new-generation nano-technology Large Scale Integrated circuits (LSI). Proposed post-silicon multi-way tuning is the mixture of clock skew tuning and body-bias tuning for improving the performance yield of LSI. The results of this research include algorithms for finding the best set of tuning values, pre-silicon design optimizations of datapath circuits which aim to maximize the maximum performance achieved by post-silicon tuning.

Free Research Field

集積回路理論