| Project/Area Number |
04555078
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | KYOTO UNIVERSITY |
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Principal Investigator |
TAMARU Keikichi Kyoto Univ., Dept.of Electronics Professor, 工学部, 教授 (10127102)
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| Co-Investigator(Kenkyū-buntansha) |
寺井 正幸 三菱電機(株), システムLSI開発技術研究所, グループマネージャー
KOBAYASHI K Kyoto Univ., Dept.of Elec.Research Asso., 工学部, 助手 (70252476)
ONODERA H Kyoto Univ., Dept.of Elec.Asso.Prof., 工学部, 助教授 (80160927)
UESAKA T Kumamoto National Col.of Tech., Dept.of Info.Prof., 情報工学科, 教授 (30213333)
YASUURA H Kyushu Univ., Dept.of Info.Systems Prof., 大学院・総合理工学研究科, 教授 (80135540)
TERAI M Mitsubishi Electric Corp., System LSI Lab.Group Manager
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| Project Period (FY) |
1992 – 1994
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| Project Status |
Completed (Fiscal Year 1994)
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| Budget Amount *help |
¥15,900,000 (Direct Cost: ¥15,900,000)
Fiscal Year 1994: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 1993: ¥7,600,000 (Direct Cost: ¥7,600,000)
Fiscal Year 1992: ¥7,600,000 (Direct Cost: ¥7,600,000)
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| Keywords | Design rule check / LSI layout / Layout verification / Hardware engine / Parallel Processing / Content addressable memory / Geometrical processing / 図形演算 / ハードウエアエンジン |
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| Research Abstract |
The objective of this research is that we should develop a specific computer which performs geometrical-figure processing very rapidly. The geometrical-figure processing is the primitive function in the current LSI design. It comprises logical, topological and geometrical operations and also area/length calculation.
This research aimed to dissolve the bottle-neck in the current LSI design process by that specific computer.
The results of this research are as follows
1.Acceleration of parallel processing in LSI design rule check (DRC)
2.Development of a computer system specific to LSI DRC
3.A method of DRC by functional partitioning.
4.Development of a functional memory type parallel processor.
We constructed a computer system to evaluate the above results. A host computer which controls all processor elements (called workers) is a standard engineering work station using 68040 processors. We developed four brand-new workers. The worker performs data input and output simultaneously using two-port memory modules. The DRC processing unit in the worker is a single-board computer which comprises a CPU called M32/100. And also we developed software packages which control the system and performs DRC.This system with two workers performs DRC twice faster than that with a single worker.
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