Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2017: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2016: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2015: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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Outline of Final Research Achievements |
We have proposed and implemented an error diagnosis technique combining BDD-based functional approaches and a SAT-solver, which makes it possible to diagnose large scale circuits including a lot of logic design errors by making use of unsatisfiable (UNSAT) cores obtained by the SAT solver. In addition, we have applied it to a flexible incremental synthesis system employing RECON (reconfigurable) cells to fix ECO’s (Engineering Change Orders) only by changing metal layer masks. The experimental results have shown that the proposed system is effective to reduce costs needed for ECO’s on large circuits with complicated structures.
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