Robust ultra-low voltage LSI design technology
| Project/Area Number |
15K06036
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Multi-year Fund |
|---|
| Section | 一般 |
|---|
| Research Field |
Electron device/Electronic equipment
|
|---|
| Research Institution | Waseda University |
|---|
Principal Investigator |
|
|---|
| Project Period (FY) |
2015-04-01 – 2018-03-31
|
| Project Status |
Completed (Fiscal Year 2017)
|
| Budget Amount *help |
¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2017: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2016: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2015: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
|
|---|
| Keywords | ロバスト / 低電圧回路 / 低消費電力回路 / LSI設計 / ソフトエラー耐性 |
|---|
| Outline of Final Research Achievements |
As semiconductor technology continues scaling down, the reliability issue has become much more critical than ever before. Robust ultra-low voltage LSIs are presented in this research. Bulk-type circuit and FinFET-type circuit are developed. Experimental results show they reduce leak power by 15-30%. Unlike traditional hard-errors caused by permanent physical damage which can’t be recovered in field, soft errors are caused by radiation or voltage/current fluctuations that lead to transient changes on internal node states, thus they can be viewed as temporary errors. However, due to the unpredictable occurrence of soft errors, it is desirable to develop soft error tolerant designs. In this research, low-power soft error tolerant New-SHE latch, Fast-SEH latch, and SHC latch is proposed. In case of SHC latch, 80.52% power reduction at maximum is achieved compared with HiPeR latch, and 66.04% delay reduction at maximum is achieved compared with FERST latch.
|
Report
(4 results)
Research Products
(5 results)
