Study on Stochastic Flash A-to-D Converter Design and Its Implementation
| Project/Area Number |
15K06048
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Communication/Network engineering
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| Research Institution | Kitami Institute of Technology |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
吉澤 真吾 北見工業大学, 工学部, 准教授 (20447080)
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| Project Period (FY) |
2015-04-01 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2017: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2016: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2015: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | 確率的フラッシュAD変換器 / 一様確率密度関数の合成 / 線形化 / 量子化雑音の無相関化 / 設計理論 / 回路シミュレーション / 統計的アナログ信号処理 / 確率密度関数の合成 / 動的素子整合法 / 動的素子整合手法 / 偶高調波ミクサ / 時間-デジタル変換器 / ΔΣ変調器 / 時間‐デジタル変換器 |
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| Outline of Final Research Achievements |
We have proposed a design methodology for "Stochastic Flash A-to-D Converter (SFADC)", which is known as a kind of high-speed ADC, robust against processing variations under nanoscale integration.
First, we clarified the issues in comparators for SFADC and showed its design procedure. Then we proposed a linearization method to synthesize uniform distribution from the distribution of threshold voltages of comparators. In SFADC, we at the first time pointed out that decorrelation of quantization noise is important and proposed a decorrelation method and its circuit implementation. We designed the SFADC, with the above proposed mtehods, as an LSI and verified by
circuit simulation for the effectiveness of the proposed design method.
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Report
(4 results)
Research Products
(27 results)
