Design Space Exploration of Future Microprocessors using the post CMOS devices
| Project/Area Number |
15K12000
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | Tohoku University |
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Principal Investigator |
EGAWA Ryusuke 東北大学, サイバーサイエンスセンター, 准教授 (80374990)
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| Co-Investigator(Renkei-kenkyūsha) |
Kobayashi Hiroaki 東北大学, 情報科学研究科, 教授 (40205480)
Takizawa Hiroyuki 東北大学, サイバーサイエンスセンター, 教授 (70323996)
Tada Jubee 山形大学, 理工学研究科, 助教 (30361273)
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| Research Collaborator |
Sato Masayuki
Uno Wataru
Toyoshima Takuya
Sakai Zentaro
Ogasawara Daisuke
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| Project Period (FY) |
2015-04-01 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
Fiscal Year 2016: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2015: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Keywords | CNFET / 3次元積層 / STT-RAM / メモリ / ウェーブパイプライン / CNT / キャッシュメモリ / 配線遅延 |
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| Outline of Final Research Achievements |
In this research, for realizing a high energy efficiency microprocessor using novel device technologies in the post-Moore's era, expected to be practical around 2025, we have worked on circuits and memory subsystems designs. Regarding the circuit design, we worked on the design method of wave-pipelined circuits using CNFET. For the memory subsystem, we focus on a die stacking and STT-RAM technologies. We have examined the cache-bypass mechanism, the energy efficient data allocation method for the multi-bank memory, and the power-aware controlling mechanism for STT-RAM last-level caches.
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Report
(4 results)
Research Products
(7 results)
