LSI Design Method for Minimum Energy Operation

• Project/Area Number: 16H01713
• Research Category: Grant-in-Aid for Scientific Research (A)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system
• Research Institution: Kyoto University
• Principal Investigator: Onodera Hidetoshi 京都大学, 情報学研究科, 教授 (80160927)
• Co-Investigator(Kenkyū-buntansha): 塩見 準 京都大学, 情報学研究科, 助教 (40809795) ; 石原 亨 名古屋大学, 情報学研究科, 教授 (30323471) ; 土谷 亮 京都大学, 情報学研究科, 助教 (20432411)
• Project Period (FY): 2016-04-01 – 2020-03-31
• Project Status: Completed (Fiscal Year 2020)
• Budget Amount: ¥41,470,000 (Direct Cost: ¥31,900,000、Indirect Cost: ¥9,570,000); Fiscal Year 2019: ¥10,530,000 (Direct Cost: ¥8,100,000、Indirect Cost: ¥2,430,000); Fiscal Year 2018: ¥8,190,000 (Direct Cost: ¥6,300,000、Indirect Cost: ¥1,890,000); Fiscal Year 2017: ¥8,190,000 (Direct Cost: ¥6,300,000、Indirect Cost: ¥1,890,000); Fiscal Year 2016: ¥14,560,000 (Direct Cost: ¥11,200,000、Indirect Cost: ¥3,360,000)
• Keywords: 最小エネルギー動作 / 低消費電力設計 / 低電圧動作 / 動的電圧制御 / 基板電圧制御 / 消費エネルギー最小化 / オンチップモニタ / 電子デバイス・機器 / 省エネルギー / ディペンダブル・コンピューティング / 低消費電力技術

Outline of Final Research Achievements

We have developed a method for deriving a set of supply voltage and threshold voltage that enables the circuit to operate at the minimum energy consumption under a wide range of operating conditions and a specified delay constraint. We experimentally confirmed using a fabricated 32-bit processor that the derived set of supply voltage and threshold voltage can operate the circuit with less than 5 % excess energy from the minimum energy consumption under a wide variety of delay constraints and operating conditions. We also developed a DLL-type body bias generator that generate P/N well-voltages independently so that the energy consumption becomes minimum, which was verified by fabricated test chips.

Academic Significance and Societal Importance of the Research Achievements

集積回路内のトランジスタは、加わる電圧により強反転状態と弱反転状態に大別される。従来、最小エネルギー動作を与える電源電圧としきい値電圧の値は、動作領域ごとに別々に求められてきた。本研究では、動作状態によらずに閉形式の形で求めることに成功した。これにより、動作電圧や環境が大きく変動する状況においても、集積回路が最小エネルギで動作するように電源電圧やしきい値電圧を連続して調節することが可能となった。本技術により、所定の動作速度を達成しつつ最小の消費エネルギーで回路を動作させる事が可能となった点に大きな社会的意義がある。

Research Products

• [Journal Article] A DLL-based Body Bias Generator with Independent P-well and N-well Biasing for Minimum Energy Operation (2021)
  • Author(s): Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera
  • Journal Title: IEICE Trans. on Electronics, Volume: Vol. E104
  • NAID: 130008095562
  • Peer Reviewed / Open Access
• [Journal Article] A Design Method of a Cell-Based Amplifier for Body Bias Generation (2019)
  • Author(s): KOYANAGI Takuya、SHIOMI Jun、ISHIHARA Tohru、ONODERA Hidetoshi
  • Journal Title: IEICE Transactions on Electronics Volume: E102.C Issue: 7 Pages: 565-572
  • DOI: 10.1587/transele.2018CTP0014
  • NAID: 130007671364
  • ISSN: 0916-8524, 1745-1353
  • Year and Date: 2019-07-01
  • Peer Reviewed / Open Access
• [Journal Article] Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation (2019)
  • Author(s): Islam A.K.M. Mahfuzul、Onodera Hidetoshi
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Volume: 12 Issue: 0 Pages: 2-12
  • DOI: 10.2197/ipsjtsldm.12.2
  • NAID: 130007603207
  • ISSN: 1882-6687
  • Peer Reviewed / Open Access
• [Journal Article] Minimum Energy Point Tracking with All-Digital On-Chip Sensors (2018)
  • Author(s): Shiomi Jun、Hokimoto Shu、Ishihara Tohru、Onodera Hidetoshi
  • Journal Title: Journal of Low Power Electronics Volume: 14 Issue: 2 Pages: 227-235
  • DOI: 10.1166/jolpe.2018.1561
  • Peer Reviewed / Open Access
• [Journal Article] A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator (2018)
  • Author(s): Kishimoto Tadashi、Ishihara Tohru、Onodera Hidetoshi
  • Journal Title: Japanese Journal of Applied Physics Volume: 57 Issue: 4S Pages: 04FF09-04FF09
  • DOI: 10.7567/jjap.57.04ff09
  • NAID: 210000148923
  • Peer Reviewed / Open Access
• [Journal Article] A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation (2017)
  • Author(s): Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
  • Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Volume: E100.A Issue: 12 Pages: 2764-2775
  • DOI: 10.1587/transfun.E100.A.2764
  • NAID: 130006236534
  • ISSN: 0916-8508, 1745-1337
  • Peer Reviewed / Open Access
• [Journal Article] Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing (2017)
  • Author(s): Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
  • Journal Title: Integration, the VLSI Journal Volume: N/A Pages: 201-210
  • DOI: 10.1016/j.vlsi.2017.07.001
  • Peer Reviewed / Open Access
• [Presentation] A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias (2020)
  • Author(s): Kentaro Nagai, Jun Shiomi and Hidetoshi Onodera
  • Organizer: 2020 the 16th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
  • Int'l Joint Research
• [Presentation] Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region (2020)
  • Author(s): Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
  • Organizer: 2020 IEEE International SOC Conference (SOCC)
  • Int'l Joint Research
• [Presentation] Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators (2019)
  • Author(s): A.K.M. Mahfuzul Islam, Ryota Shimizu, Hidetoshi Onodera
  • Organizer: 2019 IEEE International Reliability Physics Symposium (IRPS)
  • Int'l Joint Research
• [Presentation] PVT^2: Process, Voltage, Temperature and Time-dependent Variability in Scaled CMOS Process (2018)
  • Author(s): A.K.M. Mahfuzul Islam and Hidetoshi Onodera
  • Organizer: IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN
  • Int'l Joint Research / Invited
• [Presentation] Independent N-well and P-well Biasing for Minimum Leakage Energy Operation (2018)
  • Author(s): Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera
  • Organizer: The International Symposium on On-Line Testing and Robust System Design
  • Int'l Joint Research
• [Presentation] On-Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation (2018)
  • Author(s): Tadashi Kishimoto, Tohru Ishihara and Hidetoshi Onodera
  • Organizer: International Conference on Microelectronic Test Structures
  • Int'l Joint Research
• [Presentation] Process Variation Aware D-Flip-Flop Design using Regression Analysis (2018)
  • Author(s): Shinichi Nishizawa, Hidetoshi Onodera
  • Organizer: International Symposium on Quality Electronic Design
  • Int'l Joint Research
• [Presentation] A Statistical Modeling Methodology of RTN Gate Size Dependency Based on Skewed Ring Oscillators (2017)
  • Author(s): A.K.M. Mahfuzul Islam, Tatsuya Nakai, Hidetoshi Onodera
  • Organizer: 2017 IEEE International Conference on Microelectronic Test Structures
  • Place of Presentation: Grenoble(France)
  • Year and Date: 2017-03-27
  • Int'l Joint Research
• [Presentation] Effect of supply voltage on random telegraph noise of transistors under switching condition (2017)
  • Author(s): A.K.M. Mahfuzul Islam, Hidetoshi Onodera
  • Organizer: 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
  • Int'l Joint Research
• [Presentation] A Temperature Monitor Circuit with Small Voltage Sensitivity using a Topology Reconfigurable Ring Oscillator (2017)
  • Author(s): Tadashi Kishimotoy, Tohru Ishiharay, and Hidetoshi Onodera
  • Organizer: 2017 International Conference on Solid State Devices and Materials
  • Int'l Joint Research
• [Presentation] On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator (2017)
  • Author(s): Tadashi Kishimoto, Tohru Ishihara, and Hidetoshi Onodera
  • Organizer: 2017 International Symposium on VLSI Design, Automation and Test
  • Int'l Joint Research
• [Presentation] On-Chip Temperature Sensing using a Reconfigurable Ring Oscillator (2016)
  • Author(s): Tadashi Kishimoto, Hidetoshi Onodera
  • Organizer: The 20th Workshop on Synthesis And System Integration of Mixed Information technologies
  • Place of Presentation: KRP(京都)
  • Year and Date: 2016-10-24
  • Int'l Joint Research
• [Presentation] A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory (2016)
  • Author(s): Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
  • Organizer: The 20th Workshop on Synthesis And System Integration of Mixed Information technologies
  • Place of Presentation: KRP(京都)
  • Year and Date: 2016-10-24
  • Int'l Joint Research
• [Presentation] Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing (2016)
  • Author(s): Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
  • Organizer: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
  • Place of Presentation: Bremen(Germany)
  • Year and Date: 2016-09-21
  • Int'l Joint Research