| Budget Amount *help |
¥16,900,000 (Direct Cost: ¥13,000,000、Indirect Cost: ¥3,900,000)
Fiscal Year 2018: ¥3,120,000 (Direct Cost: ¥2,400,000、Indirect Cost: ¥720,000)
Fiscal Year 2017: ¥6,110,000 (Direct Cost: ¥4,700,000、Indirect Cost: ¥1,410,000)
Fiscal Year 2016: ¥7,670,000 (Direct Cost: ¥5,900,000、Indirect Cost: ¥1,770,000)
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| Outline of Final Research Achievements |
In this research, we have proposed a novel microprocessor architecture that supports gate-level fine-grained pipeline structure for superconductor single-flux-quantum (SFQ) computing. We have successfully demonstrated a design of 48 GHz 5.6mW ultra-high-speed 8-bit SFQ multiplier by gate-level pipelining. The design results have been presented in 2019 IEEE International Solid-State Circuits Conference (ISSCC) that is one of the biggest conference focusing on semiconductor technologies. In addition to such prototype design, a 4-bit SFQ microprocessor has been designed, and we have confirmed its correct operation on circuit simulations. The SFQ microprocessor operates on 30 GHz that cannot be achieved by using traditional CMOS circuits.
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