High-performance and Low-Power Memory Management for the Era of Many-Channel Memories
| Project/Area Number |
16H06613
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| Research Category |
Grant-in-Aid for Research Activity Start-up
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system
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| Research Institution | Tohoku University |
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Principal Investigator |
Sato Masayuki 東北大学, 情報科学研究科, 助教 (50781308)
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| Research Collaborator |
Kobayashi Hiroaki
Egawa Ryusuke
Toyoshima Takuya
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| Project Period (FY) |
2016-08-26 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥2,990,000 (Direct Cost: ¥2,300,000、Indirect Cost: ¥690,000)
Fiscal Year 2017: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2016: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Keywords | メモリシステム / メモリ / 低消費電力化 / アドレスマッピング / 計算機システム |
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| Outline of Final Research Achievements |
This project proposes the high-performance and low-power management mechanism for many-channel memories, which is realized by the address-mapping schemes that limit the number of accessed channels, and the memory controller that can switch the address-mapping schemes.
The proposed address-mapping schemes change where the channel address is taken from bits of the physical address. These schemes successfully limit the number of channels accessed by executing applications, and the performance/power trade-off can be selected by switching these schemes.
The proposed memory controller can dynamically switch the address-mapping schemes. It also realizes the migration of the application data to maintain the consistency of the data placement when switching the address-mapping schemes. The evaluation results show that the memory controller can be realized by the reasonable costs of hardware and data migration.
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Report
(3 results)
Research Products
(2 results)
