• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

High-performance and Low-Power Memory Management for the Era of Many-Channel Memories

Research Project

Project/Area Number 16H06613
Research Category

Grant-in-Aid for Research Activity Start-up

Allocation TypeSingle-year Grants
Research Field Computer system
Research InstitutionTohoku University

Principal Investigator

Sato Masayuki  東北大学, 情報科学研究科, 助教 (50781308)

Research Collaborator Kobayashi Hiroaki  
Egawa Ryusuke  
Toyoshima Takuya  
Project Period (FY) 2016-08-26 – 2018-03-31
Project Status Completed (Fiscal Year 2017)
Budget Amount *help
¥2,990,000 (Direct Cost: ¥2,300,000、Indirect Cost: ¥690,000)
Fiscal Year 2017: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2016: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Keywordsメモリシステム / メモリ / 低消費電力化 / アドレスマッピング / 計算機システム
Outline of Final Research Achievements

This project proposes the high-performance and low-power management mechanism for many-channel memories, which is realized by the address-mapping schemes that limit the number of accessed channels, and the memory controller that can switch the address-mapping schemes.
The proposed address-mapping schemes change where the channel address is taken from bits of the physical address. These schemes successfully limit the number of channels accessed by executing applications, and the performance/power trade-off can be selected by switching these schemes.
The proposed memory controller can dynamically switch the address-mapping schemes. It also realizes the migration of the application data to maintain the consistency of the data placement when switching the address-mapping schemes. The evaluation results show that the memory controller can be realized by the reasonable costs of hardware and data migration.

Report

(3 results)
  • 2017 Annual Research Report   Final Research Report ( PDF )
  • 2016 Annual Research Report
  • Research Products

    (2 results)

All 2017

All Presentation (2 results) (of which Int'l Joint Research: 2 results)

  • [Presentation] An Application-adaptive Data Allocation Method for Multi-channel Memory2017

    • Author(s)
      Takuya Toyoshima, Masayuki Sato, Ryusuke Egawa and Hiroaki Kobayashi
    • Organizer
      IEEE Symposium on Low-Power and High-Speed Chips
    • Place of Presentation
      Yokohama Joho Bunka Center, Yokohama, Japan
    • Year and Date
      2017-04-19
    • Related Report
      2016 Annual Research Report
    • Int'l Joint Research
  • [Presentation] An Application-adaptive Data Allocation Method for Multi-channel Memory2017

    • Author(s)
      Takuya Toyoshima, Masayuki Sato, Ryusuke Egawa, and Hiroaki Kobayashi
    • Organizer
      Proceedings of IEEE International Symposium on High-Performance and Low-Power Chips (COOL Chips 20)
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research

URL: 

Published: 2016-09-02   Modified: 2019-03-29  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi