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Research on Test and Diagnosis for Delay Faults by Accurate Delay Fault Simulator

Research Project

Project/Area Number 16K00075
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Computer system
Research InstitutionEhime University

Principal Investigator

Higami Yoshinobu  愛媛大学, 理工学研究科(工学系), 教授 (40304654)

Co-Investigator(Kenkyū-buntansha) 高橋 寛  愛媛大学, 理工学研究科(工学系), 教授 (80226878)
王 森レイ  愛媛大学, 理工学研究科(工学系), 講師 (90735581)
Project Period (FY) 2016-04-01 – 2020-03-31
Project Status Completed (Fiscal Year 2019)
Budget Amount *help
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2018: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2017: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2016: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
KeywordsLSIのテスト / 故障診断 / 遅延故障 / LSIテスト / マルチサイクルテスト / 縮退故障 / 信号伝搬遅延変動 / テストパターン数削減 / ブリッジ故障 / 故障シミュレーション
Outline of Final Research Achievements

In this research, we have discussed the problems on test and diagnosis considering signal propagation delay in LSIs. We have developed efficient methods on three different issues as described below. First, we have developed a fault diagnosis method for bridging faults between a gate signal line and a clock signal line. The second issue is on the fault diagnosis under multi-cycle test environment with considering signal delay variation. The third issue is on test pattern reduction for field diagnosis.

Academic Significance and Societal Importance of the Research Achievements

LSI(大規模集積回路)のテストや故障診断は,LSIおよびそれが組み込まれた機器の高信頼化において非常に重要な技術である.本研究では,特に,信号伝搬遅延が変動した場合にも,テストや故障診断が高精度で行えるような手法を開発した.近年の高速処理を行うLSIでは,わずかな信号伝搬遅延の変動が大きな影響を与えるため,本研究で開発した手法の学術的意義が増している.

Report

(5 results)
  • 2019 Annual Research Report   Final Research Report ( PDF )
  • 2018 Research-status Report
  • 2017 Research-status Report
  • 2016 Research-status Report
  • Research Products

    (12 results)

All 2019 2018 2017 2016 Other

All Int'l Joint Research (3 results) Journal Article (1 results) (of which Int'l Joint Research: 1 results,  Peer Reviewed: 1 results) Presentation (8 results) (of which Int'l Joint Research: 6 results,  Invited: 3 results)

  • [Int'l Joint Research] University of Wisconsin - Madison(米国)

    • Related Report
      2018 Research-status Report
  • [Int'l Joint Research] University of Wisconsin - Madison(米国)

    • Related Report
      2017 Research-status Report
  • [Int'l Joint Research] University of Wisconsin - Madison(米国)

    • Related Report
      2016 Research-status Report
  • [Journal Article] A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line2017

    • Author(s)
      Y. Higami, S. Wang, H. Takahashi, S. Kobayashi and K. K. Saluja
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E100.D Issue: 9 Pages: 2224-2227

    • DOI

      10.1587/transinf.2016EDL8210

    • NAID

      130006038431

    • ISSN
      0916-8532, 1745-1361
    • Related Report
      2017 Research-status Report
    • Peer Reviewed / Int'l Joint Research
  • [Presentation] 圧縮故障辞書を用いたフィールド故障診断2019

    • Author(s)
      中村 友和, 稲元 勉, 王 森レイ, 樋上 喜信, 高橋 寛
    • Organizer
      電気関係学会四国支部連合大会
    • Related Report
      2019 Annual Research Report
  • [Presentation] Adaptive Field Diagnosis for Reducing Computing Time2018

    • Author(s)
      Yoshinobu Higami
    • Organizer
      International Conference on Fuzzy Systems and Data Mining
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] Fault Diagnosis Considering Path Delay Variations in Multi Cycle Test Environment2018

    • Author(s)
      Yoshinobu Higami, Tsutomu Inamoto, Senling Wang, Hiroshi Takahashi, Kewal K Saluja
    • Organizer
      International Technical Conference on Circuits/Systems, Computers and Communications
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] Test Generation Methods for Delay Faults on Clock Lines2017

    • Author(s)
      Y. Higami
    • Organizer
      The 3rd International Conference on Fuzzy Systems and Data Mining
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] Fault Simulation using Hazard Signals and Its Application to Fault Diagnosis for Delay Faults2017

    • Author(s)
      Y. Higami
    • Organizer
      International Conference for Top and Emerging Computer Scientists
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] Adaptive Field Diagnosis for Reducing the Number of Test Patterns2017

    • Author(s)
      Y. Higami, S. Wang, H. Takahashi and K. K. Saluja
    • Organizer
      International Technical Conference on Circuits/Systems, Computers and Communications
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] マルチサイクルテストにおけるクロック信号線のd-故障に対するテストパターン生成について2016

    • Author(s)
      和田祐介, 樋上喜信, 王森レイ, 高橋寛, 小林真也
    • Organizer
      電気関係学会四国支部連合大会
    • Place of Presentation
      徳島大学(徳島県徳島市)
    • Year and Date
      2016-09-17
    • Related Report
      2016 Research-status Report
  • [Presentation] Multi-Cycle Test Diagnosis for Path Delay Variations2016

    • Author(s)
      Y. Higami, S. Wang, H. Takahashi, S. Kobayashi and K. K. Saluja
    • Organizer
      Taiwan and Japan Conference on Circuits and Systems
    • Place of Presentation
      Tainan, Taiwan
    • Year and Date
      2016-07-31
    • Related Report
      2016 Research-status Report
    • Int'l Joint Research

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Published: 2016-04-21   Modified: 2022-02-21  

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