• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

Memory access optimizations for VLSI design with high-level synthesis

Research Project

Project/Area Number 16K00084
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Computer system
Research InstitutionTokyo City University

Principal Investigator

SETO Kenshu  東京都市大学, 理工学部, 講師 (10420241)

Project Period (FY) 2016-04-01 – 2020-03-31
Project Status Completed (Fiscal Year 2019)
Budget Amount *help
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2018: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2017: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2016: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Keywords高位合成 / メモリアクセス最適化 / スカラリプレイス / メモリ分割 / システムオンチップ
Outline of Final Research Achievements

High-level synthesis significantly reduces the hardware design time, however, manual rewriting of C code is often necessary. In this research, we proposed automatic memory access optimization techniques that push the envelope of the previous techniques. According to the experimental results, the proposed method achieved 2.8x performance enhancement with 35% chip area reduction. We published 3 reviewed journal papers, one of which received the IPSJ TSLDM best paper award.

Academic Significance and Societal Importance of the Research Achievements

ソフトウェアを自動でハードウェア化する高位合成技術が、性能向上、低消費電力化のために活用されているが、画像処理や行列演算などメモリアクセスが頻繁なソフトウェアは、そのまま高位合成しても性能向上が難しく、ソフトウェアの人手最適化を行うために長時間の手間が必要となっていた。本研究では、ソフトウェア中のメモリアクセス自動最適化技術の開発に成功した。この結果、開発者がソフトウェアのハードウェア化によるメリットを享受しやすくなる。

Report

(5 results)
  • 2019 Annual Research Report   Final Research Report ( PDF )
  • 2018 Research-status Report
  • 2017 Research-status Report
  • 2016 Research-status Report
  • Research Products

    (11 results)

All 2020 2019 2018 2017 2016

All Journal Article (4 results) (of which Peer Reviewed: 4 results,  Open Access: 3 results) Presentation (7 results) (of which Int'l Joint Research: 3 results,  Invited: 1 results)

  • [Journal Article] Shift Register Initialization in Scalar Replacement for Reducing Code Size2020

    • Author(s)
      Kenshu Seto
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology

      Volume: 13 Issue: 0 Pages: 2-9

    • DOI

      10.2197/ipsjtsldm.13.2

    • NAID

      130007803330

    • ISSN
      1882-6687
    • Related Report
      2019 Annual Research Report
    • Peer Reviewed / Open Access
  • [Journal Article] Area Reduction Technique for Digital Circuit Part in Non-Binary Analog-to-Digital Converter2019

    • Author(s)
      Shindo Yuji、Seto Kenshu、San Hao
    • Journal Title

      IEEJ Transactions on Electronics, Information and Systems

      Volume: 139 Issue: 1 Pages: 76-82

    • DOI

      10.1541/ieejeiss.139.76

    • NAID

      130007542148

    • ISSN
      0385-4221, 1348-8155
    • Year and Date
      2019-01-01
    • Related Report
      2018 Research-status Report
    • Peer Reviewed
  • [Journal Article] Scalar Replacement with Circular Buffers2019

    • Author(s)
      Seto Kenshu
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology

      Volume: 12 Issue: 0 Pages: 13-21

    • DOI

      10.2197/ipsjtsldm.12.13

    • NAID

      130007603116

    • ISSN
      1882-6687
    • Related Report
      2018 Research-status Report
    • Peer Reviewed / Open Access
  • [Journal Article] Message from the Editor-in-Chief2019

    • Author(s)
      Kenshu Seto
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology

      Volume: 12 Issue: 0 Pages: 1-1

    • DOI

      10.2197/ipsjtsldm.12.1

    • NAID

      130007603027

    • ISSN
      1882-6687
    • Related Report
      2017 Research-status Report
    • Peer Reviewed / Open Access
  • [Presentation] Simultaneous Application of Memory Partitioning and Scalar Replacement2019

    • Author(s)
      Yuji Toda, Kenshu Seto
    • Organizer
      TJCAS 2019
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Small Memory Footprint Neural Network Accelerators2019

    • Author(s)
      Kenshu Seto, Hamid Nejatollahi, Jiyoung A, Sujin Kang, Nikil Dutt
    • Organizer
      International Symposium on Quality Electronic Design (ISQED)
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] 高位合成における多重ループに対するパイプライン処理時のサイクル数オーバーヘッド削減を行うループ平坦化ツールの開発2018

    • Author(s)
      石川 大輔, 瀬戸 謙修
    • Organizer
      電子情報通信学会 VLD研究会
    • Related Report
      2017 Research-status Report
  • [Presentation] Scalar Replacement with Array Dataflow Analysis for Hardware Synthesis2017

    • Author(s)
      Kenshu Seto
    • Organizer
      Forum on specification & Design Languages (FDL) 2017
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] β展開に基づくAD変換器のルックアップテーブル除去によるデジタル回路部の面積削減2017

    • Author(s)
      進藤 佑司, 瀬戸 謙修, 傘 昊
    • Organizer
      デザインガイア2017
    • Related Report
      2017 Research-status Report
  • [Presentation] 高位合成によるアクセラレータ設計を対象としたサイクル数削減およびバッファサイズ最小化のためのデータ転送最適化手法2016

    • Author(s)
      石川 大輔, 瀬戸 謙修
    • Organizer
      デザインガイア2016
    • Place of Presentation
      立命館大学 茨木キャンパス (大阪府)
    • Year and Date
      2016-11-30
    • Related Report
      2016 Research-status Report
  • [Presentation] 計算と通信を同時に行うハードウェアを生成するメモリアクセス最適化技術2016

    • Author(s)
      石川 大輔, 瀬戸 謙修
    • Organizer
      第29回 回路とシステムワークショップ
    • Place of Presentation
      北九州国際会議場(福岡県)
    • Year and Date
      2016-05-12
    • Related Report
      2016 Research-status Report

URL: 

Published: 2016-04-21   Modified: 2021-02-19  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi