| Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2018: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2017: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2016: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Outline of Final Research Achievements |
A method to estimate side channel attack (SCA) vulnerability of cryptographic circuit from design information of IC was developed. The SCA vulnerability was simulated for an FPGA-implemented AES circuit and agreed with the measurement results accurately. Next, for establishing an SCA vulnerability design method, a theoretical formula that expresses the side channel information leakage (SCIL) intensity with the SNR of the leakage trace is verified by experiments, and its effectiveness is confirmed. Furthermore, the SCIL band of the AES circuit was derived and confirmed to be consistent with the experimental results, suggesting that the SCA vulnerability design method can be established based on the formula and the equivalent circuit model of FPGA power distribution circuit. Finally, we developed an electromagnetic interference source estimation method applying the SCA method and accurately estimated the interference intensities caused by individual interference sources.
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