Vulnerability simulation of cryptographic circuit to side-channel attacks based on IC design information
| Project/Area Number |
16K00186
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Information security
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| Research Institution | Okayama University |
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Principal Investigator |
Iokibe Kengo 岡山大学, 自然科学研究科, 助教 (10420499)
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| Project Period (FY) |
2016-04-01 – 2019-03-31
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| Project Status |
Completed (Fiscal Year 2018)
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| Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2018: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2017: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2016: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Keywords | 情報セキュリティ / 暗号 / セキュリティ評価 / 耐タンパー性 / 等価回路モデル / 漏洩源推定 / 相関解析 / セキュリティ評価・監査 |
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| Outline of Final Research Achievements |
A method to estimate side channel attack (SCA) vulnerability of cryptographic circuit from design information of IC was developed. The SCA vulnerability was simulated for an FPGA-implemented AES circuit and agreed with the measurement results accurately. Next, for establishing an SCA vulnerability design method, a theoretical formula that expresses the side channel information leakage (SCIL) intensity with the SNR of the leakage trace is verified by experiments, and its effectiveness is confirmed. Furthermore, the SCIL band of the AES circuit was derived and confirmed to be consistent with the experimental results, suggesting that the SCA vulnerability design method can be established based on the formula and the equivalent circuit model of FPGA power distribution circuit. Finally, we developed an electromagnetic interference source estimation method applying the SCA method and accurately estimated the interference intensities caused by individual interference sources.
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| Academic Significance and Societal Importance of the Research Achievements |
暗号技術はIoT機器の情報セキュリティにおいて重要な役割を期待されるが、十分なセキュリティを実現するためにはハードウェアレベルでの安全性が不可欠である。本成果は、暗号ハードウェアのサイドチャネル攻撃耐性設計を製品開発の初期段階で実現することを可能にする。それにより暗号ハードウェア設計の低コスト化を実現でき、その結果、IoT機器の情報セキュリティ向上が期待できる。
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Report
(4 results)
Research Products
(8 results)
