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Circuit Wiring Design Method for Preventing the Oscillatory False Triggering of GaN Power Devices

Research Project

Project/Area Number 16K06223
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Power engineering/Power conversion/Electric machinery
Research InstitutionOkayama University

Principal Investigator

Hiraki Eiji  岡山大学, 自然科学研究科, 教授 (20284268)

Co-Investigator(Kenkyū-buntansha) 梅谷 和弘  岡山大学, 自然科学研究科, 助教 (60749323)
Project Period (FY) 2016-04-01 – 2019-03-31
Project Status Completed (Fiscal Year 2018)
Budget Amount *help
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2018: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2017: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2016: ¥2,860,000 (Direct Cost: ¥2,200,000、Indirect Cost: ¥660,000)
KeywordsGaNデバイス / 連鎖的誤動作 / コモンソースインダクタンス / 発振回路 / パワーデバイス / GaN / 発振 / 誤動作 / パワーエレクトロニクス / 次世代スイッチングデバイス / 異常発振 / ドライブ回路
Outline of Final Research Achievements

Ultra-high-speed, low on-resistance GaN-FETs are attracting attention as next-generation power semiconductor devices, and are becoming essential for the development of small-sized, high-efficiency power supplies. However, since high speed operation is possible, there is a concern about increase in noise. Since the GaN-FET has a low on-off threshold voltage, it is prone to malfunction. Since this malfunction may destroy the GaN-FET itself, it is a major obstacle to the industrial application of the GaN-FET.
In this research, we focused on the chain-like malfunction peculiar to GaN-FET, clarified the relationship between the malfunction mechanism and the circuit parasitic inductance, and developed the circuit wiring design method that can make full use of the high-speed switching characteristics possessed by GaN.

Academic Significance and Societal Importance of the Research Achievements

次世代パワー半導体素子として超高速かつ低オン抵抗のGaN-FETが注目されているが,誤動作が産業応用に対する大きな障害となっている。本研究は,GaNデバイスの連鎖的誤動作の発生原理を解明し,適切な回路設計によって誤動作を抑制することが可能であることを示した。このことは,GaNデバイスの普及に向けた大きな前進である。

Report

(4 results)
  • 2018 Annual Research Report   Final Research Report ( PDF )
  • 2017 Research-status Report
  • 2016 Research-status Report
  • Research Products

    (6 results)

All 2019 2017

All Journal Article (2 results) (of which Peer Reviewed: 2 results) Presentation (4 results) (of which Int'l Joint Research: 3 results)

  • [Journal Article] Prevention of Oscillatory False Triggering of GaN-FETs by Balancing Gate-Drain Capacitance and Common-Source Inductance2019

    • Author(s)
      Kazuhiro Umetan ; Ryunosuke Matsumoto ; Eiji Hiraki
    • Journal Title

      IEEE Transactions on Industry Applications

      Volume: 55 Issue: 1 Pages: 610-619

    • DOI

      10.1109/tia.2018.2868272

    • Related Report
      2018 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Straightforward Measurement Method of Common Source Inductance for Fast Switching Semiconductor Devices Mounted on Board2017

    • Author(s)
      Kazuhiro Umetani; Kyota Aikawa; Eiji Hiraki
    • Journal Title

      IEEE Transactions on Industrial Electronics

      Volume: 64 Pages: 8258-8267

    • Related Report
      2017 Research-status Report
    • Peer Reviewed
  • [Presentation] Measurement of the Common Source Inductance of Typical Switching Device Packages2017

    • Author(s)
      Kyota Aikawa, Tomohumi Shiida, Ryunosuke Matsumoto, Kazuhiro Umetani, Eiji Hiraki
    • Organizer
      IEEE IFEEC 2017-eccE ASIA
    • Place of Presentation
      台湾
    • Year and Date
      2017-06-03
    • Related Report
      2016 Research-status Report
    • Int'l Joint Research
  • [Presentation] Measurement of the common source inductance of typical switching device packages2017

    • Author(s)
      Kyota Aikawa; Tomohumi Shiida; Ryunosuke Matsumoto; Kazuhiro Umetani; Eiji Hiraki
    • Organizer
      2017 IEEE 3rd International Future Energy Electronics Conference and ECCE Asia (IFEEC 2017 - ECCE Asia)
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] Evaluation of impact of parasitic magnetic coupling in PCB layout on common source inductance of surface mounted package2017

    • Author(s)
      Ryunosuke Matsumoto; Kyota Aikawa; Akihiro Konishi; Kazuhiro Umetami; Eiji Hiraki
    • Organizer
      2017 IEEE 12th International Conference on Power Electronics and Drive Systems (PEDS)
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] Optimization of the balance between the gate-drain capacitance and the common source inductance for preventing the oscillatory false triggering of fast switching GaN-FETs2017

    • Author(s)
      Rynosuke Matsumoto; Kazuhiro Umetani; Eiji Hiraki
    • Organizer
      2017 IEEE Energy Conversion Congress and Exposition (ECCE)
    • Related Report
      2017 Research-status Report

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Published: 2016-04-21   Modified: 2020-03-30  

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