Quasi-quantitative characterization of defect density in SiC substrate after thermal oxidation by photo-assited capacitance measurement
Project/Area Number |
16K14227
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Research Category |
Grant-in-Aid for Challenging Exploratory Research
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Allocation Type | Multi-year Fund |
Research Field |
Electronic materials/Electric materials
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Research Institution | The University of Tokyo |
Principal Investigator |
Kita Koji 東京大学, 大学院工学系研究科(工学部), 准教授 (00343145)
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Project Period (FY) |
2016-04-01 – 2018-03-31
|
Project Status |
Completed (Fiscal Year 2017)
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Budget Amount *help |
¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2017: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2016: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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Keywords | 電子・電気材料 / 表面・界面物性 / 半導体物性 / 電子デバイス・機器 / 光照射 / 炭化ケイ素 / 界面準位密度 / インピーダンス解析 / 欠陥準位 / 光吸収 |
Outline of Final Research Achievements |
Reduction of defect state density in the energy range corresponding to semiconductor’s bandgap is inevitable for the operation of MOS devices, however, for the wide-bandgap semiconductors including SiC, the defect states locating in near-interface oxide, and those with the energy level near the middle of the bandgap often overlooked in conventional characterization techniques using MOS capacitors, due to a significantly long time constant of the electron emission from those states. We proposed an alternative method to estimate the profiles of such defect states at SiC MOS interfaces, based on the analysis of the carrier capturing process by voltage bias sweep just after the removal of the trapped carriers by irradiation of monochromatic ultraviolet or visible light. Using this method, we also clarified the difference of deep defect level profiles at SiC MOS interface formed by different oxidation processes of SiC.
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Report
(3 results)
Research Products
(34 results)