3D stacked assembly of SiC cascode power devices

Research Project

Project/Area Number	17H03214
Research Category	Grant-in-Aid for Scientific Research (B)
Allocation Type	Single-year Grants
Section	一般
Research Field	Power engineering/Power conversion/Electric machinery
Research Institution	University of Yamanashi
Principal Investigator	YANO Koji 山梨大学, 大学院総合研究部, 教授 (90252014)
Co-Investigator(Kenkyū-buntansha)	松本俊山梨大学, 大学院総合研究部, 教授 (00020503) 山本真幸山梨大学, 大学院総合研究部, 助教 (00511320)
Project Period (FY)	2017-04-01 – 2020-03-31
Project Status	Completed (Fiscal Year 2019)
Budget Amount *help	¥17,550,000 (Direct Cost: ¥13,500,000、Indirect Cost: ¥4,050,000) Fiscal Year 2019: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000) Fiscal Year 2018: ¥12,870,000 (Direct Cost: ¥9,900,000、Indirect Cost: ¥2,970,000) Fiscal Year 2017: ¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
Keywords	パワーデバイス / SiC / ワイドバンドギャップ / SIT / JFET / パワーモジュール / 実装 / ワイドバンドギャップ半導体 / 電力工学 / 半導体工学
Outline of Final Research Achievements	A stacked assembly of an SiC cascode in which a low-voltage Si-MOSFET is stacked on a high-voltage SiC buried gate static induction transistor, that is, 3D stacked SiC-BGSIT cascode, was proposed and experimentally demonstrated. An ON-resistance and breakdown voltage of the 3D stacked sample were 80mΩ　and 950V at room temperature, respectively. These electrical performances satisfy a fundamental performance as an SiC-switching power device. A turn-off time and turn-on one of the 3D stacked sample are 18ns and 240ns at room temperature for a supplied voltage of 400V and load current of 10A, respectively. The relatively large turn-on time, which is caused by the small channel width in the used SiC-BGSIT chip, will improve with an optimum design of the channel width.
Academic Significance and Societal Importance of the Research Achievements	提案した３Ｄ実装SiCカスコード素子を、電源回路やインバータなどの電力変換回路に用いれば、同システムの小型化、低損失化に貢献できる。また従来のSiC-MOSFETにおける課題であった、しきい電圧変動などの課題を克服でき、電力変換システムの高信頼・高寿命化が期待できる。