Process Variation Estimation using Flip-Flop Retention Characteristics
| Project/Area Number |
17K12657
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | Fukuoka University (2019)
Saitama University (2017-2018) |
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Principal Investigator |
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| Project Period (FY) |
2017-04-01 – 2020-03-31
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| Project Status |
Completed (Fiscal Year 2019)
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| Budget Amount *help |
¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2019: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2018: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2017: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
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| Keywords | フリップフロップ / 記憶保持特性 / ばらつき評価回路 / トランジスタ特性ばらつき / プロセスモニタ / 集積回路 / ばらつきモニタ / テスト / BIST |
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| Outline of Final Research Achievements |
Extraction method of process variation has been proposed. Retention characteristics of DFF is newly introduced to the process variation estimation since it has a good sensitivity to the balance of pfet and nfet. Proposed technique can utilize scan-chains designed for scan-tests, thus this technique has an ability to extract the amount of process variation without adding extra test purpose circuit.
Test structures are implemented into silicon chips and result shows the proposed technique can estimate global variation shift from measured data.
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| Academic Significance and Societal Importance of the Research Achievements |
集積回路は今日の情報化社会を支える基幹部品であり，高性能化，省電力化，低価格化が強く望まれている．そのため集積回路の製造プロセスの微細化が急激に進められてきたが製造工程の複雑化によって製造プロセスに起因するトランジスタ特性ばらつきが問題となっている．ばらつき量はチップごとの異なるため，個々のチップのばらつき量を評価する事で電源電圧および基板電圧を調節しばらつきを補償する事が可能である．ばらつき量の測定のために測定回路を追加する事は集積回路のコストを増大させる課題がある．
本技術は既存の構造をばらつき量推定に利用する事で，追加コスト無く個々のチップのばらつき量の推定を可能にする．
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Report
(4 results)
Research Products
(4 results)
