| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2019: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2018: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2017: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
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| Outline of Final Research Achievements |
In this research, we developed a design automation system to realize LSI circuits with high reliability to which Programmable Delay Elements (PDEs) are inserted and in which malfunction due to delay variation and aging can be recovered. To reduce power consumption compared with existing design methods for PDE insertion, we proposed a new structure of PDEs and a clustering method which reduces the number of inserted PDEs. Moreover, the design time of the proposed method was about 100 times faster than that of an existing method by modifying the design processes. In computational experiments, the yield was improved and the overheads of the circuit area and the power consumption were restrained, compared with the existing method.
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