Development of Design Methodology for LSI Circuits with Tolerance for Delay Variation and Aging
| Project/Area Number |
17K12661
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | The University of Aizu |
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Principal Investigator |
Kohira Yukihide 会津大学, コンピュータ理工学部, 上級准教授 (00549298)
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| Project Period (FY) |
2017-04-01 – 2020-03-31
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| Project Status |
Completed (Fiscal Year 2019)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2019: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2018: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2017: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
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| Keywords | 集積回路設計自動化 / 遅延ばらつき / 経年劣化 / 歩留まり改善 / 遅延調整可能素子 / クロック同期回路 |
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| Outline of Final Research Achievements |
In this research, we developed a design automation system to realize LSI circuits with high reliability to which Programmable Delay Elements (PDEs) are inserted and in which malfunction due to delay variation and aging can be recovered. To reduce power consumption compared with existing design methods for PDE insertion, we proposed a new structure of PDEs and a clustering method which reduces the number of inserted PDEs. Moreover, the design time of the proposed method was about 100 times faster than that of an existing method by modifying the design processes. In computational experiments, the yield was improved and the overheads of the circuit area and the power consumption were restrained, compared with the existing method.
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| Academic Significance and Societal Importance of the Research Achievements |
PDEにより各記憶素子に供給されるクロックタイミングを調整することで回路を誤動作から回復させることができるため，本研究によりLSIの設計技術の信頼性の向上に貢献した．また，設計に掛かる時間を既存研究より100倍程度高速化したことで，大規模な回路への適用の可能性が高まり，実用性を向上した．なお，開発した設計支援システムは，アプリケーションを限定していないため，どのようなアプリケーションに対しても高信頼な集積回路を実現できることが期待される．
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Report
(4 results)
Research Products
(6 results)
