Radiation-hardened Design for Low-power Supercomputers

• Project/Area Number: 17K14667
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Electron device/Electronic equipment
• Research Institution: Kyoto Institute of Technology
• Principal Investigator: Furuta Jun 京都工芸繊維大学, 電気電子工学系, 助教 (30735767)
• Project Period (FY): 2017-04-01 – 2020-03-31
• Project Status: Completed (Fiscal Year 2019)
• Budget Amount: ¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000); Fiscal Year 2019: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000); Fiscal Year 2018: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000); Fiscal Year 2017: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
• Keywords: ソフトエラー / 重イオン / フリップフロップ / SEU / 低電力

Outline of Final Research Achievements

We measured single event upsets (SEUs) in a 65 nm FDSOI process by heavy ion irradiation tests. SEU rates on a latch on a flip-flop depend on clock frequency and delay time of a combinational logic since SEU on slave latches cannot propagate through the combinational logic before clock signal turn to "1". SEU rates at 480 MHz are 2x - 4x smaller than those at 500 kHz.
We also proposed radiation-hardened flip-flop which is based on guard gate structure. Propsed flip-flop achieves 100 times higher soft error resilience.

Academic Significance and Societal Importance of the Research Achievements

従来のソフトエラー対策では全てのフリップフロップにエラー対策を施すために、過剰な対策かつ回路の消費電力の増加が極めて大きくなっていた。しかし本研究成果により、組み合わせ回路の遅延時間が大きいフリップフロップのエラーはその遅延時間によりエラーの伝播が阻害されることを示した。この組み合わせ回路の遅延時間による除去効果を考慮してソフトエラー対策を施すことで、全てのフリップフロップにエラー対策を施した場合と同等のソフトエラー耐性を実現しつつ消費電力を抑えることが可能となる。

Research Products

• [Journal Article] Radiation-Hardened Structure to Reduce Sensitive Range of a Stacked Structure for FDSOI (2019)
  • Author(s): K. Yamada, M. Ebara, K. Kojima, Y. Tsukita, J. Furuta, and K. Kobayashi
  • Journal Title: IEEE Transactions on Nuclear Science Volume: 1 Issue: 7 Pages: 1-1
  • DOI: 10.1109/tns.2019.2908722
  • Peer Reviewed
• [Presentation] Evaluation of Soft-Error Tolerance by Neutrons and Heavy Ions on Flip Flops with Guard Gates in a 65 nm Thin BOX FDSOI Process (2019)
  • Author(s): M. Ebara, K. Yamada, K. Kojima, Y. Tsukita, J. Furuta, and K. Kobayashi
  • Organizer: Radiation and its Effects on Components and Systems
  • Int'l Joint Research
• [Presentation] Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process (2019)
  • Author(s): J. Furuta, Y. Tsukita, K. Yamada, M. Ebara, K. Kojima, and K. Kobayashi
  • Organizer: IEEE International Reliability Physics Symposium
  • Int'l Joint Research
• [Presentation] Evaluation of Heavy-Ion-Induced SEU Cross Sections of a 65 nm Thin BOX FD-SOI Flip-Flops Based on Stacked Inverter (2018)
  • Author(s): J. Furuta, K. Kojima, and K. Kobayashi
  • Organizer: The conference on Radiation and its Effects on Components and Systems
  • Int'l Joint Research
• [Patent(Industrial Property Rights)] D-type Flip-flop Circuit (2019)
  • Inventor(s): 小林和淑, 古田潤, 山田晃大
  • Industrial Property Rights Holder: 小林和淑, 古田潤, 山田晃大
  • Industrial Property Rights Type: 特許
  • Filing Date: 2019
  • Overseas