| Project/Area Number |
17K14684
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Communication/Network engineering
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| Research Institution | The University of Tokyo (2018-2019)
Tokyo University of Science (2017) |
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Principal Investigator |
Xu Zule 東京大学, 大学院工学系研究科(工学部), 特任講師 (50778925)
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| Project Period (FY) |
2017-04-01 – 2020-03-31
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| Project Status |
Completed (Fiscal Year 2019)
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| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2019: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2018: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2017: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
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| Keywords | 周波数シンセサイザ / 無線機 / IoT / 極低消費電力PLL / 位相同期回路 / 電子デバイス・機器 |
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| Outline of Final Research Achievements |
The main objective is to achieve both extremely low power consumption and low phase noise of a frequency synthesizer (PLL). DTC-based injection-lock PLL and SPD-based PLL were proposed, fabricated, and measured. Based on these results, we proposed and prototyped a DTC-and-SPD-based fractional-N PLL with lock range correction. It expects to achieve 2.8-ps rms jitter and 0.45-mW power consumption. It is possible to achieve both extremely low power consumption and low phase noise. We also proposed a wideband oscillator, a fast startup method, an ADC-based phase detector, and a spur-reduction dual-loop PLL.
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| Academic Significance and Societal Importance of the Research Achievements |
周波数シンセサイザ (PLL) について、低位相雑音にしながら従来リング型PLLの数10-mW以上定常消費電力をsub-mWレベルまで低減できた。広ループ帯域幅でリング発振器位相雑音を抑えるため、その効果、ノイズの抑制だけではなく、PLLの起動時間も大幅に短縮可能となった。逐次比較高速起動手法を加え、間欠動作に合わせて更なる低消費電力化が可能となる。他の提案した広帯域発振器、新規位相検出器とspur抑制手法も含め、本研究で創出した技術は、極低消費電力IoT無線機に応用可能と考える。将来の大規模センサネットワークの普及に役に立つことを期待できる。
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