Nano-structure functional devices based Ge-based channels
Project/Area Number |
18063005
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Research Category |
Grant-in-Aid for Scientific Research on Priority Areas
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Allocation Type | Single-year Grants |
Review Section |
Science and Engineering
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Research Institution | The University of Tokyo |
Principal Investigator |
TAKAGI Shinichi The University of Tokyo, 大学院・工学系研究科, 教授 (30372402)
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Co-Investigator(Kenkyū-buntansha) |
SUGAHARA Satoshi 東京工業大学, 理工学研究科附属像情報工学研究施設, 准教授 (40282842)
竹中 充 東京大学, 大学院・工学系研究科, 准教授 (20451792)
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Co-Investigator(Renkei-kenkyūsha) |
TAKENAKA Mitsuru 東京大学, 大学院・工学系研究科, 准教授 (20451792)
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Project Period (FY) |
2006 – 2009
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Project Status |
Completed (Fiscal Year 2009)
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Budget Amount *help |
¥108,400,000 (Direct Cost: ¥108,400,000)
Fiscal Year 2009: ¥28,100,000 (Direct Cost: ¥28,100,000)
Fiscal Year 2008: ¥28,100,000 (Direct Cost: ¥28,100,000)
Fiscal Year 2007: ¥26,100,000 (Direct Cost: ¥26,100,000)
Fiscal Year 2006: ¥26,100,000 (Direct Cost: ¥26,100,000)
|
Keywords | ゲルマニウム / MOSFET / GOI / 移動度 / 面方位 / スピン / 強磁性 |
Research Abstract |
In order to realize high performance Ge devices, (110)-oriented Ge-On-Insulator structures have been realized and high hole mobility pMOSFETs have been fabricated on the structures. Also, the formation and the evaluation of thermal oxidation GeO2/Ge MOS structures have revealed the superior MOS interfaces with low density of interface states. In addition, high electron and hole mobility have been realized in MOSFETs using this interface. Also, the effectiveness of atomic hydrogen annealing has been demonstrated for reducing the leakage current of Ge devices. The development of half-metal Source/Drain technologies for Ge MOSFETs using full heusler alloys has been conducted. A method of rapid thermal annealing for epitaxial Ge/ultrathin SOI/buried oxide/Si has been proposed and has realized highly-ordered Go2FeGe layers.
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Report
(6 results)
Research Products
(155 results)
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[Journal Article] Carrier-transport-enhanced channel CMOS for improved power consumption and performance2008
Author(s)
S. Takagi, T. Irisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka, N. Sugiyama
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Journal Title
IEEE Trans. Electron Devices Vol.55,No.1
Pages: 21-39
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[Journal Article] Carrier-transport-enhanced channel CMOS for improved power consumption and performance2008
Author(s)
S. Takagi, T. Irisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka and N. Sugiyama
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Journal Title
IEEE Trans. Electron Devices(Invited Paper) Vol. 55, No. 1
Pages: 21-39
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[Journal Article] Carrier-transport-enhanced channel CMOS for improved power consumption and performance (lnvited Paper)2008
Author(s)
S. Takagi, T. lrisawa, T. Tezuka, T.Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka and N. Sugiyama
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Journal Title
IEEE Transaction on Electron Devices 55
Pages: 21-39
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Peer Reviewed
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[Journal Article] Mobility- Enhanced Device Technologies Using SiGe/Ge MOS Channels2007
Author(s)
S. Takagi, T. Irisawa, T. Tezuka, S. Nakaharai, T. Numata, N. Hirashita, Y. Moriyama, K. Usuda, S. Dissanayake, M. Tekenaka, S. Sugahara, N. Sugiyama
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Journal Title
ECS Trans. Vol.11,No.6
Pages: 61-74
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[Journal Article] Gate Dielectric Formation and MIS Interface Characterization on Ge2007
Author(s)
S. Takagi, T. Maeda, N. Taoka, M. Nishizawa, Y. Morita, K. Ikeda, Y. Yamashita, M. Nishikawa, H. Kumagai, R. Nakane, S. Sugahara, N. Sugiyama
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Journal Title
Microelectronic Engineering vol.84,Issue9-10
Pages: 2314-2319
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[Journal Article] Mobility- Enhanced Device Technologies Using SiGe/Ge MOS Channels2007
Author(s)
S. Takagi, T. Irisawa, T. Tezuka, S. Nakaharai, T. Numata, N. Hirashita, Y. Moriyama, K. Usuda, S. Dissanayake, M. Tekenaka, S. Sugahara and N. Sugiyama
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Journal Title
ECS Trans. Vol. 11, No. 6
Pages: 61-74
Related Report
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[Journal Article] Gate Dielectric Formation and MIS Interface Characterization on Ge2007
Author(s)
S. Takagi, T. Maeda, N. Taoka, M. Nishizawa, Y. Morita, K. Ikeda, Y. Yamashita, M. Nishikawa, H. Kumagai, R. Nakane, S. Sugahara and N. Sugiyama
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Journal Title
Microelectronic Engineering vol. 84, Issue 9-10
Pages: 2314-2319
Related Report
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[Journal Article] Mobility-Enhanced Device Technologies Using SiGe/Ge MOS Channels2007
Author(s)
S. Takagi, T. Irisawa, T. Tezuka, S. Nakaharai, T. Numata, N. Hirashita, Y. Moriyama, K. Usuda, S. Dissanayake, M. Tekenaka, S. Sugahara and N. Sugiyama
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Journal Title
ECS Transaction 11
Pages: 61-74
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[Journal Article] Gate Dielectric Formation and MIS interface Characterization on Ge2007
Author(s)
S. Takagi, T. Maeda, N. Taoka, M. Nishizawa, Y. Morita, K lkeda, Y. Yamashita, M. Nishikawa, H. Kumagai, R. Nakane, S. Sugahara and N. Sugiyama
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Journal Title
Microelectronic Engineering 84
Pages: 2314-2319
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Peer Reviewed
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[Presentation] Ge/III-V Channel Engineering for future CMOS2009
Author(s)
S.Takagi, M.Sugiyama, T.Yasuda, M.Takenaka
Organizer
1st International Symposium on Graphene and Emerging Materials for Post-CMOS Applications, 215th Meeting of The Electrochemical Society
Place of Presentation
San Francisco, USA
Year and Date
2009-05-25
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[Presentation] Understanding and Control of Ge MIS Interface Properties (invited)2007
Author(s)
S. Takagi, T. Maeda, N. Taoka, M. Nishizawa, Y. Morita, K. Ikeda, Y. Yamashita, M. Harada, T. Yamamoto, N. Sugiyama, M. Nishikawa, H. Kumagai, H. Matsubara, R. Nakane, M. Takenaka and S. Sugahara
Organizer
4th International Symposium on Advanced Gate Stack Technology
Place of Presentation
Dallas, USA
Year and Date
2007-09-27
Related Report
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[Presentation] Gate Dielectric Formation and MIS interface Characteriation on Ge(invited)2007
Author(s)
S. Takagi, T. Maeda, N. Taoka, M. Nishizawa, Y. Morita, K. lkeda, Y. Yamashita, M. Nishikawa, H. Kumagai, R. Nakane, S. Sugahara and N. Sugiyama
Organizer
15th lnsulating Films on Semiconductors(INFOS2007)
Place of Presentation
Athens, Greece
Year and Date
2007-06-23
Related Report
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[Presentation] Gate Dielectric Formation and MIS Interface Characterization on Ge (invited)2007
Author(s)
S. Takagi, T. Maeda, N. Taoka, M. Nishizawa, Y. Morita, K. Ikeda, Y. Yamashita, M. Nishikawa, H. Kumagai, R. Nakane, S. Sugahara, N. Sugiyama
Organizer
15th Insulatring Films on Semiconductors (INFOS2007)
Place of Presentation
Athens, Greece
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[Presentation] Examination of Additive Mobility Enhancements for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs2007
Author(s)
O. Weber, T. Irisawa, T. Numata, M. Harada, N. Taoka, Y. Yamashita, T. Yamamoto, N. Sugiyama, M. Takenaka, S. Takagi
Organizer
International Electron Device Meeting
Place of Presentation
Washington DC., USA
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[Presentation] Gate Dielectric Formation and MIS Interface Characterization on Ge (invited)2007
Author(s)
S. Takagi, T. Maeda, N. Taoka, M. Nishizawa, Y. Morita, K. Ikeda, Y. Yamashita, M. Nishikawa, H. Kumagai, R. Nakane, S. Sugahara and N. Sugiyama
Organizer
15th Insulatring Films on Semiconductors (INFOS2007), pp. 2314-2319
Place of Presentation
Athens, Greece
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[Presentation] Prospects and Critical Issues on Ge MOS Technologies (invited)2006
Author(s)
S. Takagi, N. Taoka, S. Nakaharai, K. Ikeda, T. Tezuka, Y. Yamashita, Y. Moriyama, T. Maeda, N. Sugiyama
Organizer
SiGe & Ge: Materials, Processing, and Devices Symposium, the 2006 Joint International Electrochemical Society Meeting
Place of Presentation
Moon Palace Resort, Cancun, Mexico(invited)
Year and Date
2006-10-29
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[Presentation] Mobility-Enhanced Device Technologies Using SiGe/Ge MOS Channels (invited)2006
Author(s)
S. Takagi, T. Tezuka, T. Irisawa, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, K. Ikeda, N. Taoka, Y. Yamashita, M. Harada, T. Maeda, T. Yamamoto, N. Sugiyama
Organizer
2nd Int. Workshop on New Group IV Semiconductor Nanoelectronics
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