Deep Learning Processor for Pipelined Backpropagation
Project/Area Number |
18H01500
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Research Category |
Grant-in-Aid for Scientific Research (B)
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Allocation Type | Single-year Grants |
Section | 一般 |
Review Section |
Basic Section 21060:Electron device and electronic equipment-related
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Research Institution | Kobe University |
Principal Investigator |
KAWAGUCHI Hiroshi 神戸大学, 科学技術イノベーション研究科, 教授 (00361642)
|
Project Period (FY) |
2018-04-01 – 2021-03-31
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Project Status |
Completed (Fiscal Year 2021)
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Budget Amount *help |
¥16,900,000 (Direct Cost: ¥13,000,000、Indirect Cost: ¥3,900,000)
Fiscal Year 2020: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2019: ¥11,570,000 (Direct Cost: ¥8,900,000、Indirect Cost: ¥2,670,000)
Fiscal Year 2018: ¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
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Keywords | 深層学習 / 低消費電力プロセッサ / SRAM / ニューラルネットワーク / ディープラーニング / ディープラーニングプロセッサ |
Outline of Final Research Achievements |
Dual-port SRAM for a deep learning processor was implemented in a 28nm FD-SOI process. It was confirmed that the energy consumption required for the read operation of image data can be reduced by 14.76%. This technology was expanded in a 20-transistor ultra-multiport SRAM for codebook quantization in a deep learning processor; a prototype 4k-bit codebook that functions as a lookup table to convert 8 bits to 16 bits was fabricated in a 40nm process. The codebook reduced energy by 20% and area by 26% in the motif processor, NVIDIA NVDLA.
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Academic Significance and Societal Importance of the Research Achievements |
IoTデバイスの低エネルギ画像認識の需要は機械学習により様々な分野で拡大している。カメラの高解像度化に反して、低エネルギ処理とリアルタイム性維持の両立が求められている。深層学習プロセッサは大量のパラメータと入出力を扱うため、大容量の内部SRAMが必要となり、シリコン面積の50%以上を占め、エネルギは外部DRAM帯域に支配される。精度を落とさずにメモリ帯域を削減する方法として量子化がある。コードブック方式は任意の非線形関数を表現でき、線形量子化よりも精度劣化を抑えることができる。この用途のために深層学習プロセッサのコードブック量子化用20トランジスタ超多ポートSRAMを設計、試作した。
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Report
(4 results)
Research Products
(12 results)
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[Journal Article] A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor with Selective Sourceline Drive Scheme2019
Author(s)
H. Mori, T. Nakagawa, Y. Kitahara, Y. Kawamoto, K. Takagi, S. Yoshimoto, S. Izumi, H. Kawaguchi, and M. Yoshimoto 97.H. Mori, T. Nakagawa, Y. Kitahara, Y. Kawamoto, K. Takagi, S. Yoshimoto, S. Izumi, H. Kawaguchi, and M. Yoshimoto
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Journal Title
IEEE Transactions on Circuits and Systems I
Volume: 印刷中
NAID
Related Report
Peer Reviewed
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[Presentation] R. Kawamoto, M. Taichi, M. Kabuto, D. Watanabe, S. Izumi, M. Yoshimoto, and H. Kawaguchi, "A 1.15-TOPS 6.57-TOPS/W DNN Processor for Multi-Scale Object Detection2020
Author(s)
R. Kawamoto, M. Taichi, M. Kabuto, D. Watanabe, S. Izumi, M. Yoshimoto, and H. Kawaguchi
Organizer
IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)
Related Report
Int'l Joint Research
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