Design methodology of noise-driven logic circuits toward ultra-low-power computing systems
| Project/Area Number |
18H03302
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Review Section |
Basic Section 61040:Soft computing-related
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| Research Institution | Hokkaido University |
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Principal Investigator |
Asai Tetsuya 北海道大学, 情報科学研究院, 教授 (00312380)
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| Project Period (FY) |
2018-04-01 – 2021-03-31
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| Project Status |
Completed (Fiscal Year 2020)
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| Budget Amount *help |
¥17,420,000 (Direct Cost: ¥13,400,000、Indirect Cost: ¥4,020,000)
Fiscal Year 2020: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2019: ¥8,060,000 (Direct Cost: ¥6,200,000、Indirect Cost: ¥1,860,000)
Fiscal Year 2018: ¥7,280,000 (Direct Cost: ¥5,600,000、Indirect Cost: ¥1,680,000)
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| Keywords | 集積回路 / 低電力論理回路 / 確率共鳴 / フローティングゲート / 論理回路 / 低電力回路 / CMOS / ノイズ |
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| Outline of Final Research Achievements |
A stochastic-resonance (SR)-based NAND gate is designed where the power consumption is decreased by ultra-low voltage supply, and the subsequent malfunction of NAND operation (due to the low voltage supply) is recovered by injecting noises to the circuit. The gate consists of two floating-gate inverters having multiple inputs where a latch circuit is constructed by the two inverters. By using threshold function of the latch, a threshold-based logic circuit (NAND) was constructed. In general, to implement functional logic functions with floating-gate technology, capacitance of the floating gates must be larger than the ground capacitance, however, the latch amplified small differences between the input floating gates, which resulted in relaxation of its input amplitudes and threshold voltages of the two floating-gate inverters.
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| Academic Significance and Societal Importance of the Research Achievements |
本研究成果を基板とした集積回路工学の発展により、長時間駆動やエナジーハーベスティング技術の恩恵を直接受けられる集積回路が実現できると思われる。また、フローティングゲートプロセスが必須になることから、我が国が得意とするフラッシュ型不揮発メモリのプロセスの強みを活かした卓越した技術・産業の基盤となり得る。集積デバイス学、回路設計学、システム設計学の分野を横断する研究成果であり、停滞気味の日本の半導体集積回路研究の活性化に向けた一助となれば幸いである。
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Report
(4 results)
Research Products
(36 results)
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[Journal Article] Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks2019
Author(s)
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M.,
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Journal Title
IEICE Transactions on Information and Systems
Volume: E102.D
Issue: 12
Pages: 2341-2353
DOI
NAID
ISSN
0916-8532, 1745-1361
Year and Date
2019-12-01
Related Report
Peer Reviewed / Open Access
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[Journal Article] BRein memory: a single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4TOPS at 0.6W2018
Author(s)
Ando K., Ueyoshi K., Orimo K., Yonekawa H., Sato S., Nakahara H., Takamaeda-Yamazaki S., Ikebe M., Asai T., Kuroda T., and Motomura M.
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Journal Title
IEEE J. Solid-State Circuits
Volume: 53
Issue: 4
Pages: 983-994
DOI
Related Report
Peer Reviewed / Open Access
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