| Budget Amount *help |
¥17,420,000 (Direct Cost: ¥13,400,000、Indirect Cost: ¥4,020,000)
Fiscal Year 2020: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2019: ¥8,060,000 (Direct Cost: ¥6,200,000、Indirect Cost: ¥1,860,000)
Fiscal Year 2018: ¥7,280,000 (Direct Cost: ¥5,600,000、Indirect Cost: ¥1,680,000)
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| Outline of Final Research Achievements |
A stochastic-resonance (SR)-based NAND gate is designed where the power consumption is decreased by ultra-low voltage supply, and the subsequent malfunction of NAND operation (due to the low voltage supply) is recovered by injecting noises to the circuit. The gate consists of two floating-gate inverters having multiple inputs where a latch circuit is constructed by the two inverters. By using threshold function of the latch, a threshold-based logic circuit (NAND) was constructed. In general, to implement functional logic functions with floating-gate technology, capacitance of the floating gates must be larger than the ground capacitance, however, the latch amplified small differences between the input floating gates, which resulted in relaxation of its input amplitudes and threshold voltages of the two floating-gate inverters.
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