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Self-Heating-Effect-Free p/n-Stacked-NW/Bulk-FinFETs and 6T-SRAM

Research Project

Project/Area Number 18K04258
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Review Section Basic Section 21060:Electron device and electronic equipment-related
Research InstitutionTokyo Institute of Technology

Principal Investigator

Hitoshi Wakabayashi  東京工業大学, 工学院, 教授 (80700153)

Co-Investigator(Kenkyū-buntansha) 宗田 伊理也  東京工業大学, 工学院, 助教 (90750018)
Project Period (FY) 2018-04-01 – 2021-03-31
Project Status Completed (Fiscal Year 2020)
Budget Amount *help
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2020: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2019: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2018: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
KeywordsNano-wire / FinFET / 自己発熱効果 / Nanowire / p/n vertical integration / Self-heating effect / Multi-input NOR / P/n vertical integration / 半導体 / MISFET / ナノワイヤ
Outline of Final Research Achievements

For MOSFET technology for ultra-low power consumption LSI, miniaturization by nano-wire (NW) structure is effective. However, the decrease in drive current due to self-heating effect is a problem, and it is effective to realize a heat dissipation path (recess contact) leading to the substrate by stacked NW on FinFETs. Therefore, we clarified the self-heating effect suppression and area reduction effect for Inverter, Transfer gate, NOR, NAND, multi-input NOR / NAND, and SRAM by p/n-stacked NW/FinFETs. Next, although the self-heating effect is more serious in NOR than in NAND, but it was clarified that the drive current is able to be maintained up to 5 inputs.

Academic Significance and Societal Importance of the Research Achievements

この成果は今後のLogic LSIの高性能化のために重要な知見であると考えられ、今後のサステナブル社会に資すると考えられる。

Report

(4 results)
  • 2020 Annual Research Report   Final Research Report ( PDF )
  • 2019 Research-status Report
  • 2018 Research-status Report
  • Research Products

    (13 results)

All 2021 2020 2019 2018

All Journal Article (3 results) (of which Open Access: 3 results,  Peer Reviewed: 2 results) Presentation (10 results) (of which Int'l Joint Research: 6 results,  Invited: 8 results)

  • [Journal Article] Hitoshi Wakabayashi Laboratory, Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology (Tokyo Tech)2021

    • Author(s)
      若林整
    • Journal Title

      Journal of The Japan Institute of Electronics Packaging

      Volume: 24 Issue: 1 Pages: 162-162

    • DOI

      10.5104/jiep.24.162

    • NAID

      130007965242

    • ISSN
      1343-9677, 1884-121X
    • Year and Date
      2021-01-01
    • Related Report
      2020 Annual Research Report
    • Open Access
  • [Journal Article] Self-heating-aware cell design for p/n-vertically-integrated nanowire on FinFET beyond 3 nm technology node2020

    • Author(s)
      Tomohiko Yamagishi, Atsushi Hori, Iriya Muneta, Kuniyuki Kakushima, Kazuo Tsutsui and Hitoshi Wakabayashi
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 59 Issue: SG Pages: SGGA09-SGGA09

    • DOI

      10.35848/1347-4065/ab6d83

    • Related Report
      2019 Research-status Report
    • Peer Reviewed / Open Access
  • [Journal Article] Relaxation of Self-Heating-Effect for Stacked-Nanowire FET and p/n-Stacked 6T-SRAM Layout2019

    • Author(s)
      Eisuke Anju, Iriya Muneta, Kuniyuki Kakushima, Kazuo Tsutsui and Hitoshi Wakabayashi
    • Journal Title

      IEEE, Journal of Electron Device Society

      Volume: 6 Pages: 1239-1245

    • DOI

      10.1109/jeds.2018.2882406

    • Related Report
      2018 Research-status Report
    • Peer Reviewed / Open Access
  • [Presentation] 将来の Natural Human I/F デバイスの実現に向けた実装技術2021

    • Author(s)
      若林整
    • Organizer
      実装フェスタ関西 2020
    • Related Report
      2020 Annual Research Report
    • Invited
  • [Presentation] Self-Heating-Aware Cell Design for Multi-Stacked Circuits with p/n-Vertically-Integrated Nanowires on FinFET2019

    • Author(s)
      T. Yamagishi, A. Hori, I. Muneta, K. Kakushima, K. Tsutsui, and H. Wakabayashi
    • Organizer
      N-1-02, pp. 557-558, Solid State Devices and Materials, Japan Society of Applied Physics
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] 横型p/n積層ナノワイヤによるNORとNANDセルの省面積設計2019

    • Author(s)
      山岸 朋彦、堀 敦、宗田 伊理也、角嶋 邦之、筒井 一生、若林 整
    • Organizer
      2019年第80回応用物理学会秋季学術講演会、18a-B11-4
    • Related Report
      2019 Research-status Report
  • [Presentation] Current Progress on 2D Materials and their FETs for Future LSIs2019

    • Author(s)
      Hitoshi Wakabayashi
    • Organizer
      SEMI China, IEEE, CSTIC 2019
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] Benchmark on Advanced Logic Devices and Predictive Discussion on Future LSIs2018

    • Author(s)
      Hitoshi Wakabayashi
    • Organizer
      The 40th anniversary of DPS 2018
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] Discussion on LSI Configurations and Performances from Process to Upper Levels2018

    • Author(s)
      Hitoshi Wakabayashi
    • Organizer
      IEEE ISSM 2019, Tutorial
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] Advanced Device Technologies beyond FinFET era for Logic Chip2018

    • Author(s)
      Hitoshi Wakabayashi
    • Organizer
      SEMI Japan 2018, STS
    • Related Report
      2018 Research-status Report
    • Invited
  • [Presentation] 総論:Si ULSIの現状と今後の動向、招待講演2018

    • Author(s)
      若林整
    • Organizer
      JSPS, 145委員会
    • Related Report
      2018 Research-status Report
    • Invited
  • [Presentation] Vertically-Stacked Nanowire/FinFETs and Following 2D FETs for Logic Chips2018

    • Author(s)
      Hitoshi Wakabayashi
    • Organizer
      IEEE, EDS, S3S 2018
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] Advanced 3D-CMOS-Device Benchmark and Sputtered-MoS2 2D-FET Operation2018

    • Author(s)
      Hitoshi Wakabayashi
    • Organizer
      22nd International Symposium on Chemical-Mechanical Planarization
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research / Invited

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Published: 2018-04-23   Modified: 2022-01-27  

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