| Project/Area Number |
18K04258
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Multi-year Fund |
|---|
| Section | 一般 |
|---|
| Review Section |
Basic Section 21060:Electron device and electronic equipment-related
|
|---|
| Research Institution | Tokyo Institute of Technology |
|---|
Principal Investigator |
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
宗田 伊理也 東京工業大学, 工学院, 助教 (90750018)
|
|---|
| Project Period (FY) |
2018-04-01 – 2021-03-31
|
| Project Status |
Completed (Fiscal Year 2020)
|
| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2020: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2019: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2018: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
|
|---|
| Keywords | Nano-wire / FinFET / 自己発熱効果 / Nanowire / p/n vertical integration / Self-heating effect / Multi-input NOR / P/n vertical integration / 半導体 / MISFET / ナノワイヤ |
|---|
| Outline of Final Research Achievements |
For MOSFET technology for ultra-low power consumption LSI, miniaturization by nano-wire (NW) structure is effective. However, the decrease in drive current due to self-heating effect is a problem, and it is effective to realize a heat dissipation path (recess contact) leading to the substrate by stacked NW on FinFETs. Therefore, we clarified the self-heating effect suppression and area reduction effect for Inverter, Transfer gate, NOR, NAND, multi-input NOR / NAND, and SRAM by p/n-stacked NW/FinFETs. Next, although the self-heating effect is more serious in NOR than in NAND, but it was clarified that the drive current is able to be maintained up to 5 inputs.
|
| Academic Significance and Societal Importance of the Research Achievements |
この成果は今後のLogic LSIの高性能化のために重要な知見であると考えられ、今後のサステナブル社会に資すると考えられる。
|
