Study on Automated Design Verification Combining a SAT-based Method and a Machine Learning Technique
| Project/Area Number |
18K11216
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Review Section |
Basic Section 60040:Computer system-related
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| Research Institution | Shimane University |
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Principal Investigator |
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| Project Period (FY) |
2018-04-01 – 2021-03-31
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| Project Status |
Completed (Fiscal Year 2020)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2020: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2019: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2018: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Keywords | カバレッジ駆動検証 / SATソルバ / 機械学習 |
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| Outline of Final Research Achievements |
The goal of this study was to improve the efficiency of coverage-driven verification, a method of design verification, by combining a method using machine learning with a method using the SAT solver, in order to automate the verification of various circuit designs.
Due to the lack of real design descriptions with input constraints and the limited performance of the machine learning tool planned to use, only a part of the original plan was achieved, but the following results were obtained:(1) improvement of the performance with an SMT solver, (2) improvement of the performance with a distributed execution method, (3) evaluation of the error detection capability for descriptions with artificially inserted errors, and (4) Establishment and validation of a coverage-driven verification method under input constraints.
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| Academic Significance and Societal Importance of the Research Achievements |
半導体回路は現代社会の基盤であり，その動作の正しさを保証する設計検証は回路の安全性を保証する上で不可欠な技術である．その設計検証の自動化・高速化を押し進める上で，本研究で得られた効率の改善手法やより現実的な入力制約を考慮した自動検証手法は必要とされており，エラー検出能力の評価は手法の実用性を担保するものである．この意味で本研究の成果は学術的また社会的に意義のあるものであると考える．
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Report
(4 results)
Research Products
(3 results)
