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Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits

Research Project

Project/Area Number 18K18026
Research Category

Grant-in-Aid for Early-Career Scientists

Allocation TypeMulti-year Fund
Review Section Basic Section 60040:Computer system-related
Research InstitutionKyushu Institute of Technology

Principal Investigator

Holst Stefan  九州工業大学, 大学院情報工学研究院, 助教 (40710322)

Project Period (FY) 2018-04-01 – 2020-03-31
Project Status Completed (Fiscal Year 2019)
Budget Amount *help
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2019: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2018: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
KeywordsVLSI / Logic Diagnosis / Small-Delay Defects / IR-Drop / Response Compression / Process Variations / Soft-Error Tolerance / GPU Computing / Failure Analysis
Outline of Final Research Achievements

This project made significant progress in collecting reliable diagnosis data from chips and enabling diagnosis of defects with complex timing behavior. Two new methods for reliably gathering test responses in the face of potential IR-drop and clock skew issues were developed. One method is based on static structural circuit analysis and the other method is based on accurate GPU-accelerated timing simulation. Furthermore, a new soft-error tolerant latch was published that enables testing and diagnosing of latch-internal production defects for the first time.
Two new diagnosis algorithms were developed. First, a new small delay fault diagnosis approach that is able to analyze highly compressed production test responses that contain the combined effects of the actual defect and omnipresent and unknown delay variations. Second, a diagnosis approach that can for the first time identify hidden delay defects to learn from early-life failures even before they occur.

Academic Significance and Societal Importance of the Research Achievements

Finding root causes of failing chips through logic diagnosis is essential to ensure and improve reliability and safety of electronic systems. This research enabled diagnosis of complex timing defects previous methods were unable to find and thus contributes to more reliable and safe systems.

Report

(3 results)
  • 2019 Annual Research Report   Final Research Report ( PDF )
  • 2018 Research-status Report
  • Research Products

    (16 results)

All 2020 2019 2018 Other

All Int'l Joint Research (4 results) Presentation (12 results) (of which Int'l Joint Research: 5 results,  Invited: 1 results)

  • [Int'l Joint Research] University of Stuttgart/University of Paderborn(ドイツ)

    • Related Report
      2019 Annual Research Report
  • [Int'l Joint Research] Anhui University, Heifei/Anhui Univ. of Science & Technology(中国)

    • Related Report
      2019 Annual Research Report
  • [Int'l Joint Research] University of Stuttgart/University of Paderborn(ドイツ)

    • Related Report
      2018 Research-status Report
  • [Int'l Joint Research] Anhui University, Heifei/Anhui Univ. of Science & Technology(中国)

    • Related Report
      2018 Research-status Report
  • [Presentation] Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses2020

    • Author(s)
      Stefan Holst
    • Organizer
      FTC Workshop Jan. 2020, Yurihama, Tottori-ken, Japan
    • Related Report
      2019 Annual Research Report
  • [Presentation] Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses2020

    • Author(s)
      Stefan Holst
    • Organizer
      South European Test Seminar 2020, Obergurgl, Austria
    • Related Report
      2019 Annual Research Report
  • [Presentation] STAHL: A Novel Scan-Test-Aware Hardened Latch Design2019

    • Author(s)
      Ruijun Ma
    • Organizer
      24th IEEE European Test Symposium (ETS) 2019
    • Related Report
      2019 Annual Research Report 2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] Small Delay Fault Diagnosis with Compacted Responses2019

    • Author(s)
      Stefan Holst
    • Organizer
      56th Design Automation Conference (DAC) 2019 Work-In-Progress Poster
    • Related Report
      2019 Annual Research Report 2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] Logic Fault Diagnosis of Hidden Delay Defects2019

    • Author(s)
      Stefan Holst
    • Organizer
      FTC Workshop Jul. 2019, Daigo-machi, Kuji-gun, Ibaraki-ken, Japan
    • Related Report
      2019 Annual Research Report
  • [Presentation] Accelerated Timing Simulation and Its Applications2019

    • Author(s)
      Stefan Holst
    • Organizer
      Dagstuhl Workshop "Intelligent Methods for Test and Reliability" Sep. 2019, Dagstuhl, Germany
    • Related Report
      2019 Annual Research Report
    • Invited
  • [Presentation] Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses2019

    • Author(s)
      Stefan Holst
    • Organizer
      IEEE International Test Conference, Nov. 2019, Washington DC, USA
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test2019

    • Author(s)
      Shiling Shi
    • Organizer
      IEEE 24th Pacific Rim International Symposium on Dependable Computing (PRDC) Dec. 2019, Kyoto, Japan
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Small Delay Fault Diagnosis with Compacted Responses2019

    • Author(s)
      Stefan Holst
    • Organizer
      FTC Workshop Jan. 2019, Kitakyushu-shi, Fukuoka-ken, Japan
    • Related Report
      2018 Research-status Report
  • [Presentation] Small Delay Fault Diagnosis with Compacted Responses2019

    • Author(s)
      Stefan Holst
    • Organizer
      South European Test Seminar 2019, St. Leonhard, Pitztal, Austria
    • Related Report
      2018 Research-status Report
  • [Presentation] Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits2018

    • Author(s)
      Stefan Holst
    • Organizer
      FTC Workshop Jul. 2018, Sakura-shi, Tochigi-ken, Japan
    • Related Report
      2018 Research-status Report
  • [Presentation] Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing2018

    • Author(s)
      Yucong Zhang
    • Organizer
      27th IEEE Asian Test Symposium (ATS) 2018
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research

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Published: 2018-04-23   Modified: 2021-02-19  

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