| Budget Amount *help |
¥19,630,000 (Direct Cost: ¥15,100,000、Indirect Cost: ¥4,530,000)
Fiscal Year 2009: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2008: ¥6,890,000 (Direct Cost: ¥5,300,000、Indirect Cost: ¥1,590,000)
Fiscal Year 2007: ¥8,840,000 (Direct Cost: ¥6,800,000、Indirect Cost: ¥2,040,000)
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| Research Abstract |
It has been recognized that a lot of problems like leakage current, delay variations, and soft-error become more serious due to shrinking device size in VLSI. In this research, we have developed an asynchronous design methodology which can tolerate any timing-related problems using the energy-efficient coding and the multi-threshold-voltage transistors. We have also developed a processor-level fault tolerance technique for dependable chip multiprocessors which will be widely used in the future technology.
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