Variation and Defect Aware Design of Integrated Circuits
| Project/Area Number |
19300010
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kyoto University |
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Principal Investigator |
ONODERA Hidetoshi Kyoto University, 情報学研究科, 教授 (80160927)
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| Co-Investigator(Kenkyū-buntansha) |
KOBAYASHI Kazutoshi 京都工芸繊維大学, 工芸科学研究科, 教授 (70252476)
TSUCHIYA Akira 京都大学, 情報学研究科, 助教 (20432411)
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| Project Period (FY) |
2007 – 2009
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| Project Status |
Completed (Fiscal Year 2009)
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| Budget Amount *help |
¥19,110,000 (Direct Cost: ¥14,700,000、Indirect Cost: ¥4,410,000)
Fiscal Year 2009: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2008: ¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2007: ¥10,270,000 (Direct Cost: ¥7,900,000、Indirect Cost: ¥2,370,000)
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| Keywords | 製造ばらつき / 製造容易化設計 / 高信頼化 / ディペンダブルVLSI / 低消費電力化 / 歩留まり / 経年劣化 / NBTI / ばらつき考慮設計 / DFM / DFY / 統計的遅延解析 / スタンダードセル / 集積回路 / ばらつき / 製造容易性 |
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| Research Abstract |
We have investigated on a design method that improves manufacturability and tolerance to variation as well as a method for compensating variation and defects. Simplification and regularity enhancement of layout patterns the effect of simplified and regularity-enhanced layouts have been quantitatively examined by simulation and real chip measurements. Vulnerability of FF timing characteristics under within-die variation has been pointed out and variation-tolerant design of FFs is proposed. On-chip monitor circuits for the estimation of die-to-die variation has been also developed.
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Report
(4 results)
Research Products
(15 results)
