Variation and Defect Aware Design of Integrated Circuits

• Project/Area Number: 19300010
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Kyoto University
• Principal Investigator: ONODERA Hidetoshi Kyoto University, 情報学研究科, 教授 (80160927)
• Co-Investigator(Kenkyū-buntansha): KOBAYASHI Kazutoshi 京都工芸繊維大学, 工芸科学研究科, 教授 (70252476) ; TSUCHIYA Akira 京都大学, 情報学研究科, 助教 (20432411)
• Project Period (FY): 2007 – 2009
• Project Status: Completed (Fiscal Year 2009)
• Budget Amount: ¥19,110,000 (Direct Cost: ¥14,700,000、Indirect Cost: ¥4,410,000); Fiscal Year 2009: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000); Fiscal Year 2008: ¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000); Fiscal Year 2007: ¥10,270,000 (Direct Cost: ¥7,900,000、Indirect Cost: ¥2,370,000)
• Keywords: 製造ばらつき / 製造容易化設計 / 高信頼化 / ディペンダブルVLSI / 低消費電力化 / 歩留まり / 経年劣化 / NBTI / ばらつき考慮設計 / DFM / DFY / 統計的遅延解析 / スタンダードセル / 集積回路 / ばらつき / 製造容易性

Research Abstract

We have investigated on a design method that improves manufacturability and tolerance to variation as well as a method for compensating variation and defects. Simplification and regularity enhancement of layout patterns the effect of simplified and regularity-enhanced layouts have been quantitatively examined by simulation and real chip measurements. Vulnerability of FF timing characteristics under within-die variation has been pointed out and variation-tolerant design of FFs is proposed. On-chip monitor circuits for the estimation of die-to-die variation has been also developed.

Research Products

• [Journal Article] Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells (2010)
  • Author(s): Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Journal Title: IPSJ Transactions on System LSI Design Methodology vol.3 Pages: 130-139
  • NAID: 130000251502
  • Peer Reviewed
• [Journal Article] Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells (2010)
  • Author(s): H.Sunagawa, H.Terada, A.Tsuchiya, K.Kobayashi, H.Onodera
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Vol. 3 Pages: 130-139
  • NAID: 130000251502
  • Peer Reviewed
• [Journal Article] Statistical Gate Delay Model for Multiple Input Switching (2009)
  • Author(s): Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
  • Journal Title: IEICE Transactions on Fundamentals vol.E92-A,no.12 Pages: 3070-3078
  • NAID: 10026861436
  • Peer Reviewed
• [Journal Article] Statistical Gate Delay Model for Multiple Input Switching (2009)
  • Author(s): Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
  • Journal Title: IEICE Transact-ions on Fundamentals E92-A Pages: 3070-3078
  • NAID: 10026861436
  • Peer Reviewed
• [Journal Article] Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis (2008)
  • Author(s): Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
  • Journal Title: IPSJ Transactions on System LSI Design Methodology 1 Pages: 116-125
  • NAID: 130002073186
  • Peer Reviewed
• [Journal Article] Manufacturability-Aware Design of Standard Cells (2008)
  • Author(s): Hirokazu Muta, Hidetoshi Onodera
  • Journal Title: IEICE Transactions on Electronics E90-A Pages: 2682-2690
  • NAID: 110007538012
  • Peer Reviewed
• [Presentation] Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability (2010)
  • Author(s): A.K.M. Mahfuzul Islam, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Organizer: TAU Workshop 2010
  • Place of Presentation: San Francisco
  • Year and Date: 2010-03-18
• [Presentation] Characterization of WID Delay Variability Using RO-array Test Structures (2009)
  • Author(s): Hidetoshi Onodera, Haruhiko Terada
  • Organizer: Proceedings 2009 8th IEEE International Conference on ASIC
  • Place of Presentation: Changsha
  • Year and Date: 2009-10-21
• [Presentation] Characterization of WID Delay Variability Using RO-array Test Structures (2009)
  • Author(s): Hidetoshi Onodera, Haruhiko Terada
  • Organizer: 2009 8th IEEE International Conference on ASIC
  • Place of Presentation: Changsha, China
  • Year and Date: 2009-10-19
• [Presentation] Variability Modeling and Impact on Design (2008)
  • Author(s): Hidetoshi Onodera
  • Organizer: 2008 International Electron Devices Meeting
  • Place of Presentation: サンフランシスコ
  • Year and Date: 2008-12-17
• [Presentation] Statistical Gate Delay Model for Multiple Input Switching (2008)
  • Author(s): Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
  • Organizer: The 13th Asia and South Pacific Design Automation Conference
  • Place of Presentation: Seoul, Korea
  • Year and Date: 2008-01-23
• [Presentation] Regularity-Enhanced Layout of Standard Cells (2007)
  • Author(s): Hidetoshi Onodera, Hiroaki Muta
  • Organizer: 2nd IEEE International Workshop on Design for Manufacturability and Yield
  • Place of Presentation: Santa Clara, CA
  • Year and Date: 2007-10-25
• [Presentation] 統計的遅延解析における遅延分布間の最大値計算手法 (2007)
  • Author(s): 寺田 晴彦, 福岡 孝之, 土谷 亮, 小野寺 秀俊
  • Organizer: DAシンポジウム2007
  • Place of Presentation: 浜松
  • Year and Date: 2007-08-29
• [Presentation] 同時スイッチングの影響を考慮した統計的遅延解析 (2007)
  • Author(s): 福岡 孝之, 土谷 亮, 小野寺 秀俊
  • Organizer: DAシンポジウム2007
  • Place of Presentation: 浜松
  • Year and Date: 2007-08-29
• [Presentation] Toward Variability-Aware Design (2007)
  • Author(s): Hidetoshi Onodera
  • Organizer: 2007 Symposium on VLSI Technology
  • Place of Presentation: Kyoto, Japan
  • Year and Date: 2007-06-13