• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

A study on the realization and application of content-addressable memory using general-purpose memory

Research Project

Project/Area Number 19300013
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionKyushu Institute of Technology

Principal Investigator

SASAO Tsutomu  Kyushu Institute of Technology, 大学院・情報工学研究院, 教授 (20112013)

Co-Investigator(Kenkyū-buntansha) 井口 幸洋  明治大学, 理工学部, 准教授 (60201307)
Co-Investigator(Renkei-kenkyūsha) IGUCHI Yukihiro  明治大学, 理工学部, 教授 (60201307)
Project Period (FY) 2007 – 2009
Project Status Completed (Fiscal Year 2009)
Budget Amount *help
¥7,930,000 (Direct Cost: ¥6,100,000、Indirect Cost: ¥1,830,000)
Fiscal Year 2009: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Fiscal Year 2008: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Fiscal Year 2007: ¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
Keywords計算機システム / 電子デバイス / CAM / アドレス変換回路 / IPアドレス / LPM / FPGA
Research Abstract

We considered logic design methods for index generation functions. An index generation function is a mathematical model for a CAM function, which efficiently finds a desired data in a large amount of data. It is one of the most important operations in the information processing. For several applications, we developed various design methods and compared them with existing methods.

Report

(4 results)
  • 2009 Annual Research Report   Final Research Report ( PDF )
  • 2008 Annual Research Report
  • 2007 Annual Research Report
  • Research Products

    (92 results)

All 2010 2009 2008 2007 Other

All Journal Article (17 results) (of which Peer Reviewed: 17 results) Presentation (69 results) Book (2 results) Remarks (4 results)

  • [Journal Article] Programmable Architectures and design methods for two-variable numeric function generators2010

    • Author(s)
      S.Nagayama, T.Sasao, J.T.Butier
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology 3

      Pages: 118-129

    • NAID

      130000251501

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Complexities of graph-based representations for elementary functions2009

    • Author(s)
      S. Nagayama, T. Sasao
    • Journal Title

      IEEE Transactions on Computers Vol.C-58,No.1

      Pages: 106-119

    • NAID

      120002441442

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] Complexities of graph-based representations for elementary functions2009

    • Author(s)
      S. Nagayama, T. Sasao
    • Journal Title

      IEEE Transactions on Computers Vol. C-58

      Pages: 106-119

    • NAID

      120002441442

    • Related Report
      2008 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Design method for numerical function generators using recursive segmentation and EVBDDs2007

    • Author(s)
      S. Nagayama, T. Sasao, J.T. Butler
    • Journal Title

      IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences Vol.E90-A,No.12

      Pages: 2752-2761

    • NAID

      110007538021

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] BDD representation for incompletely specified multipleoutput logic functions and its application to the design of LUT cascades2007

    • Author(s)
      M. Matsuura, T. Sasao
    • Journal Title

      IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences Vol.E90-A,No.12

      Pages: 2770-2777

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] On designs of radix converters using arithmetic decompositions2007

    • Author(s)
      Y. Iguchi, T. Sasao, M. Matsuura
    • Journal Title

      Journal of Multiple-Valued Logic Vol.13,No.4-6

      Pages: 503-520

    • NAID

      110004822621

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] Numerical function generators using LUT cascades2007

    • Author(s)
      T. Sasao, S. Nagayama, J.T. Butler
    • Journal Title

      IEEE Transactions on Computers Vol.56,No.6

      Pages: 826-838

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] Design methods of radix converters using arithmetic decompositions2007

    • Author(s)
      Y. Iguchi, T. Sasao, M. Matsuura
    • Journal Title

      IEICE Trans. on Information and Systems Vol.E90-D,No.6

      Pages: 905-914

    • NAID

      110007522146

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] A new equivalence relation of logic functions and its application in the design of AND-OR-EXOR networks2007

    • Author(s)
      D. Debnath, T. Sasao
    • Journal Title

      IEICE Transaction, Special Section of Discrete Mathematics and Its Applications Vol.E90-A,No.5

      Pages: 932-940

    • NAID

      110007519156

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] On the design of LPM address generators using multiple LUT Cascades on FPGAs2007

    • Author(s)
      H. Qin, T. Sasao, J.T. Butler
    • Journal Title

      International Journal of Electronics Vol.94,Issue5

      Pages: 451-467

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] A new equivalence relation of logic funtions and its application in the design of AND-OR-EXOR networks2007

    • Author(s)
      D.Debnath and T.Sasao
    • Journal Title

      IEICE Transaction, Special Section of Discrete Mathematics and Its Applications Vol.E90-A

      Pages: 932-940

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Numerical function generators using LUT cascades2007

    • Author(s)
      T.Sasao, S.Nagayama and J.T.Butler
    • Journal Title

      IEEE Transactions on Computers Vol.56

      Pages: 826-838

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Design methods of radix converters using arithmetic decompositions2007

    • Author(s)
      Y.Iguchi, T.Sasao, and M.Matsuura
    • Journal Title

      IEICE Trans.on Information and Systems Vol.E90-D

      Pages: 905-914

    • NAID

      110007522146

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Journal Article] On the design of LPM adress generators using multiple LUT Cascades on FPGAs2007

    • Author(s)
      H.Qin, T.Sasao, and J.T.Butler
    • Journal Title

      International Journal of Electronics Vol.94

      Pages: 905-914

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Journal Article] On designs of radix converters using arithmetic decompositions2007

    • Author(s)
      Y.Iguchi, T.Sasao, and M.Matsuura
    • Journal Title

      Journal of Multiple-Valued Logic Vol.13

      Pages: 503-520

    • NAID

      110004822621

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Journal Article] BDD representation for incompletely specified multiple-output logic functions and its application to the design of LUT cascades2007

    • Author(s)
      M.Matsuura and T.Sasao
    • Journal Title

      IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences Vol.E90-A

      Pages: 2770-2777

    • NAID

      110007538022

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Design method for numerical function generators using recursive segmentation and EVBDDs2007

    • Author(s)
      S.Nagayama, T.Sasao, and J.T.Butler
    • Journal Title

      IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences Vol.E90-A

      Pages: 2752-2761

    • NAID

      110007538021

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Presentation] FPGA上に実現したいくつかの近似マッチングアルゴリズムの比較に関する研究2010

    • Author(s)
      清水敬介, 中原啓貴, 笹尾勤, 松浦宗寛
    • Organizer
      電子情報通信学会VLSI設計技術研究会
    • Place of Presentation
      沖縄
    • Year and Date
      2010-03-12
    • Related Report
      2009 Final Research Report
  • [Presentation] FPGA上に実現した二つの近似文字列マッチングアルゴリズムの比較2010

    • Author(s)
      清水敬介, 中原啓貴, 笹尾勤, 松浦宗寛
    • Organizer
      電子情報通信学会VLSI設計技術研究会
    • Place of Presentation
      那覇
    • Year and Date
      2010-03-12
    • Related Report
      2009 Annual Research Report
  • [Presentation] 並列ブランチング・プログラム・マシンを用いたパケット分類器について2010

    • Author(s)
      中原啓貴, 笹尾勤, 松浦宗寛, 川村嘉郁
    • Organizer
      電子情報通信学会RECONF研究会
    • Place of Presentation
      慶応大
    • Year and Date
      2010-01-27
    • Related Report
      2009 Final Research Report
  • [Presentation] 並列ブランチング・プログラム・マシンを用いたパケット分類器について2010

    • Author(s)
      中原啓貴, 笹尾勤, 松浦宗寛, 川村嘉郁
    • Organizer
      電子情報通信学会RECONF研究会
    • Place of Presentation
      東京
    • Year and Date
      2010-01-27
    • Related Report
      2009 Annual Research Report
  • [Presentation] Smith- WatermanアルゴリズムのFPGA上への実装とその評価に関する研究2010

    • Author(s)
      清水敬介, 笹尾勤, 中原啓貴
    • Organizer
      電子情報通信学会「第23回多値論理とその応用研究会」
    • Place of Presentation
      明治大学
    • Year and Date
      2010-01-09
    • Related Report
      2009 Final Research Report
  • [Presentation] 4値CAMを用いた分類関数の実現について2010

    • Author(s)
      笹尾勤
    • Organizer
      電子情報通信学会「第23回多値論理とその応用研究会」
    • Place of Presentation
      明治大学
    • Year and Date
      2010-01-09
    • Related Report
      2009 Final Research Report
  • [Presentation] 種々の決定グラフマシンのアーキテクチャの比較について2010

    • Author(s)
      中原啓貴, 笹尾勤, 松浦宗寛
    • Organizer
      電子情報通信学会「第23回多値論理とその応用研究会」
    • Place of Presentation
      明治大学
    • Year and Date
      2010-01-09
    • Related Report
      2009 Final Research Report
  • [Presentation] 4値CAMを用いた分類関数の実現について2010

    • Author(s)
      笹尾勤
    • Organizer
      電子情報通信学会第23回多値とその応用研究会
    • Place of Presentation
      東京
    • Year and Date
      2010-01-09
    • Related Report
      2009 Annual Research Report
  • [Presentation] 種々の決定グラフマシンのアーキテクチャの比較について2010

    • Author(s)
      中原啓貴, 笹尾勤, 松浦宗寛
    • Organizer
      電子情報通信学会第23回多値とその応用研究会
    • Place of Presentation
      東京
    • Year and Date
      2010-01-09
    • Related Report
      2009 Annual Research Report
  • [Presentation] Smith-WatemanアルゴリズムのFPGA上への実装とその評価に関する研究2010

    • Author(s)
      清水敬介, 笹尾勤, 中原啓貴
    • Organizer
      電子情報通信学会第23回多値とその応用研究会
    • Place of Presentation
      東京
    • Year and Date
      2010-01-09
    • Related Report
      2009 Annual Research Report
  • [Presentation] 3アドレスQDDマシン用コードの最適アルゴリズムについて2009

    • Author(s)
      福山泰介, 笹尾勤, 松浦宗寛
    • Organizer
      電子情報通信学会RECONF研究会
    • Place of Presentation
      高知
    • Year and Date
      2009-12-04
    • Related Report
      2009 Annual Research Report 2009 Final Research Report
  • [Presentation] 並列ふるい法とMPUを用いたウイルス検出エンジンについて2009

    • Author(s)
      中原啓貴, 笹尾勤, 松浦宗寛, 川村嘉郁
    • Organizer
      電子情報通信学会RECONF研究会
    • Place of Presentation
      高知
    • Year and Date
      2009-12-03
    • Related Report
      2009 Annual Research Report 2009 Final Research Report
  • [Presentation] Logic functions for cryptography-A tutorial2009

    • Author(s)
      J.T.Butler, T.Sasao
    • Organizer
      Reed-Muller Workshop
    • Place of Presentation
      Okinawa, Japan
    • Year and Date
      2009-05-24
    • Related Report
      2009 Annual Research Report
  • [Presentation] Bent functions and their relation to switching circuit theory2009

    • Author(s)
      J.T.Butler, T.Sasao
    • Organizer
      Reed-Muller Workshop
    • Place of Presentation
      Okinawa, Japan
    • Year and Date
      2009-05-24
    • Related Report
      2009 Annual Research Report
  • [Presentation] 並列ブランチング・プログラム・マシンを用いた順序回路の模擬について2009

    • Author(s)
      中原啓貴, 笹尾勤, 松浦宗寛, 川村嘉郁
    • Organizer
      電子情報通信学会VLSI設計技術研究会
    • Place of Presentation
      那覇
    • Year and Date
      2009-03-12
    • Related Report
      2009 Final Research Report
  • [Presentation] 不完全定義インデックス生成関数の変数最小化について2009

    • Author(s)
      中村高明, 笹尾勤, 松浦宗寛
    • Organizer
      電子情報通信学会VLSI設計技術研究会
    • Place of Presentation
      那覇
    • Year and Date
      2009-03-11
    • Related Report
      2009 Final Research Report
  • [Presentation] 不完全定義インデックス生成関数の変数最小化について2009

    • Author(s)
      中村高明, 笹尾勤, 松浦宗寛
    • Organizer
      電子情報通信学会, VLSI設計技術研究会
    • Place of Presentation
      那覇市
    • Year and Date
      2009-03-11
    • Related Report
      2008 Annual Research Report
  • [Presentation] 並列プランチンク・プログラム・マシンを用いた順序回路の模擬について2009

    • Author(s)
      中原啓貴, 笹尾勤, 松浦宗寛, 川村嘉郁
    • Organizer
      電子情報通信学会, VLSI設計技術研究会
    • Place of Presentation
      那覇市
    • Year and Date
      2009-03-11
    • Related Report
      2008 Annual Research Report
  • [Presentation] A virus scanning engine using a parallel finite-input memory machines and MPUs2009

    • Author(s)
      H. Nakahara, T. Sasao, M. Matsuura, Y. Kawamura
    • Organizer
      19th International Conference on Field Programmable Logic and Applications (FPL-2009)
    • Place of Presentation
      Prague. Czech Republic
    • Related Report
      2009 Final Research Report
  • [Presentation] The Parallel sieve method for a virus scanning engine2009

    • Author(s)
      H. Nakahara, T. Sasao, M. Matsuura, Y. Kawamura
    • Organizer
      12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009)
    • Place of Presentation
      Patras, Greece
    • Related Report
      2009 Final Research Report
  • [Presentation] Representation of incompletely specified index generation functions using minimal number of compound variables2009

    • Author(s)
      T. Sasao, T. Nakamura, M. Matsuura
    • Organizer
      12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009)
    • Place of Presentation
      Patras, Greece
    • Related Report
      2009 Final Research Report
  • [Presentation] On the number of LUTS to realize sparse logic functions2009

    • Author(s)
      T. Sasao
    • Organizer
      18th International Workshop on Logic and Synthesis, (IWLS- 2009)
    • Place of Presentation
      Berkeley, CA, U.S.A.
    • Related Report
      2009 Final Research Report
  • [Presentation] LUTMIN: FPGA logic synthesis with MUX-based and cascade realizations2009

    • Author(s)
      T. Sasao, A. Mishchenko
    • Organizer
      18th International Workshop on Logic and Synthesis, (IWLS- 2009)
    • Place of Presentation
      Berkeley
    • Related Report
      2009 Final Research Report
  • [Presentation] Logic functions for cryptography- A tutorial2009

    • Author(s)
      J.T. Butler, T. Sasao
    • Organizer
      Reed-Muller Workshop (RM2009)
    • Related Report
      2009 Final Research Report
  • [Presentation] Floating-point numerical function generators using EVMDDs for monotone elementary functions2009

    • Author(s)
      S. Nagayama, T. Sasao, J.T. Butler
    • Organizer
      39th International Symposium on Multiple-Valued Logic (ISMVL 2009)
    • Related Report
      2009 Final Research Report
  • [Presentation] A quaternary decision diagram machine and the optimization of its code2009

    • Author(s)
      T. Sasao, H. Nakahara, M. Matsuura, Y. Kawamura, J.T. Butler
    • Organizer
      39th International Symposium on Multiple-Valued Logic (ISMVL 2009)
    • Related Report
      2009 Final Research Report
  • [Presentation] Emulation of sequential circuits by a parallel branching program machine2009

    • Author(s)
      H. Nakahara, T. Sasao, M. Matsuura, Y. Kawamura
    • Organizer
      5th International Workshop on Applied Reconfigurable Computing
    • Place of Presentation
      Karlsruhe, Germany
    • Related Report
      2009 Final Research Report 2008 Annual Research Report
  • [Presentation] Representation of incompletely specified index generation functions using minimal number of compound variables2009

    • Author(s)
      S.Nagayama, T.Sasao, J.T.Butler
    • Organizer
      39th International Symposium on Multiple-Valued Logic
    • Place of Presentation
      Okinawa, Japan
    • Related Report
      2009 Annual Research Report
  • [Presentation] A quaternary decision diagram machine and the optimization of its code2009

    • Author(s)
      T.Sasao, H.Nakahara, M.Matsuura, Y.Kawamura, J.T.Butler
    • Organizer
      39th International Symposium on Multiple-Valued Logic
    • Place of Presentation
      Okinawa, Japan
    • Related Report
      2009 Annual Research Report
  • [Presentation] LUTMIN : FPGA logic synthesis with MUX-based and cascade realizations2009

    • Author(s)
      T.Sasao, A.Mishchenko
    • Organizer
      18th International Workshop on Logic and Synthesis
    • Place of Presentation
      Berkeley, CA, U.S.A.
    • Related Report
      2009 Annual Research Report
  • [Presentation] On the number of LUTs to realize sparse logic functions2009

    • Author(s)
      T.Sasao
    • Organizer
      18th International Workshop on Logic and Synthesis
    • Place of Presentation
      Berkeley, CA, U.S.A.
    • Related Report
      2009 Annual Research Report
  • [Presentation] Representation of incompletely specified index generation functions using minimal number of compound variables2009

    • Author(s)
      T.Sasao, T.Nakamura, M.Matsuura
    • Organizer
      11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools
    • Place of Presentation
      Patras, Greece
    • Related Report
      2009 Annual Research Report
  • [Presentation] A parallel sieve method for the virus scanning engine2009

    • Author(s)
      H.Nakahara, T.Sasao, M.Matsuura, Y.Kawamura
    • Organizer
      11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools
    • Place of Presentation
      Patras, Greece
    • Related Report
      2009 Annual Research Report
  • [Presentation] A virus scanning engine using a parallel finite-input memory machine and MPUs2009

    • Author(s)
      H.Nakahara, T.Sasao, M.Matsuura, Y.Kawamura
    • Organizer
      19th International Conference on Field Programmable Logic and Applications
    • Place of Presentation
      Prague, Czech Republic
    • Related Report
      2009 Annual Research Report
  • [Presentation] 書換え可能な二変数関数の数値計算回路について2008

    • Author(s)
      永山忍, 笹尾勤, J.T. Butler
    • Organizer
      電子情報通信学会リコンフィギャラブルシステム研究会
    • Place of Presentation
      北九州市
    • Year and Date
      2008-11-18
    • Related Report
      2009 Final Research Report
  • [Presentation] 書換え可能な二変数関数の数値計算回路について2008

    • Author(s)
      永山忍, 笹尾勤, Jon T. Butler
    • Organizer
      電子情報通信学会, リコンフィギヤラブルシステム研究会, RECONF2008-49
    • Place of Presentation
      北九州市
    • Year and Date
      2008-11-18
    • Related Report
      2008 Annual Research Report
  • [Presentation] On the number of variables to represent sparse logic functions2008

    • Author(s)
      T. Sasao
    • Organizer
      ICCAD-2008
    • Place of Presentation
      San Jose, California, USA
    • Related Report
      2009 Final Research Report
  • [Presentation] Numerical function generators using bilinear interpolation2008

    • Author(s)
      S. Nagayama, T. Sasao, , J.T. Butler
    • Organizer
      FPL-2008
    • Place of Presentation
      Heidelberg, Germany
    • Related Report
      2009 Final Research Report
  • [Presentation] Programmable numerical function generators for two-variable functions2008

    • Author(s)
      S. Nagayama, J.T. Butler, T. Sasao
    • Organizer
      DSD 2008, 10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools
    • Place of Presentation
      Parma, Italy
    • Related Report
      2009 Final Research Report
  • [Presentation] On the complexity of single-digit error detection function in redundant residue number system2008

    • Author(s)
      T. Sasao, Y. Iguchi
    • Organizer
      10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools
    • Place of Presentation
      Parma, Italy
    • Related Report
      2009 Final Research Report
  • [Presentation] On the number of variables to represent sparse logic functions2008

    • Author(s)
      T. Sasao
    • Organizer
      17th InternationalWorkshop on Logic & Synthesis (IWLS- 2008)
    • Place of Presentation
      Lake Tahoe, California, USA
    • Related Report
      2009 Final Research Report
  • [Presentation] On the complexity of classification functions2008

    • Author(s)
      T. Sasao
    • Organizer
      International Symposium on Multiple-valued Logic (ISMVL-2008)
    • Place of Presentation
      Dallas, TX
    • Related Report
      2009 Final Research Report
  • [Presentation] Representations of two-variable elementary functions using EVMDDs and their applications to function generators2008

    • Author(s)
      S. Nagayama, T. Sasao
    • Organizer
      International Symposium on Multiple-valued Logic (ISMVL-2008)
    • Place of Presentation
      Dallas, TX
    • Related Report
      2009 Final Research Report
  • [Presentation] メモリ構造をしたプログラム可能論理素子とその応用2008

    • Author(s)
      笹尾勤
    • Organizer
      電子情報通信学会2008総合全国大会
    • Place of Presentation
      北九州学術研究都市
    • Related Report
      2009 Final Research Report
  • [Presentation] On the complexity of classification functions2008

    • Author(s)
      T. Sasao
    • Organizer
      International Symposium on Multiple-valued Logic (ISMVL-2008)
    • Place of Presentation
      Dallas, TX, USA
    • Related Report
      2008 Annual Research Report
  • [Presentation] Representations of two-variable elementary functions using EVMDDs and their applications to function generators2008

    • Author(s)
      S. Nagayama, T. Sasao
    • Organizer
      International Symposium on Multiple-valued Logic (ISMVL-2008)
    • Place of Presentation
      Dallas, TX, USA
    • Related Report
      2008 Annual Research Report
  • [Presentation] On the number of variables to represent sparse logic funotions2008

    • Author(s)
      T. Sasao
    • Organizer
      17th International Workshop on Logic & Synthesis (IWLS-2008)
    • Place of Presentation
      Lake Tahoe, California, USA
    • Related Report
      2008 Annual Research Report
  • [Presentation] Programmable numerical function generators for two-variable functions2008

    • Author(s)
      S. Nagayama, J. T. Butler, T. Sasao
    • Organizer
      10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools(DSD 2008)
    • Place of Presentation
      Parma, Italy
    • Related Report
      2008 Annual Research Report
  • [Presentation] On the complexity of single-digit error detection function in redundant residue number system2008

    • Author(s)
      T. Sasao, Y. Iguchi
    • Organizer
      10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools(DSD2008)
    • Place of Presentation
      Parma, Italy
    • Related Report
      2008 Annual Research Report
  • [Presentation] Numerical function generators using bilinear interpolation2008

    • Author(s)
      S. Nagayama, T. Sasao, J. T. Butler
    • Organizer
      The International Conference on Field Programmable Logic and Applications (FPL-2008)
    • Place of Presentation
      Heidelberg, Germany
    • Related Report
      2008 Annual Research Report
  • [Presentation] On the number of variables to represent sparse logic functions2008

    • Author(s)
      T. Sasao
    • Organizer
      The 2008 International Conference on Computer-Aided Design (ICCAD-2008)
    • Place of Presentation
      San Jose, California, USA
    • Related Report
      2008 Annual Research Report
  • [Presentation] The eigenfunction of the Reed-Muller transformation2007

    • Author(s)
      T. Sasao, J.T. Butler
    • Organizer
      RM- 2007
    • Place of Presentation
      Oslo, Norway
    • Year and Date
      2007-05-16
    • Related Report
      2009 Final Research Report
  • [Presentation] Implementations of reconfigurable logic arrays on FPGAs2007

    • Author(s)
      T. Sasao, H. Nakahara
    • Organizer
      International Conference on Field-Programmable Technology 2007 (ICFPT'07)
    • Place of Presentation
      Kitakyushu, Japan
    • Related Report
      2009 Final Research Report
  • [Presentation] An implementation of an address generator using hash memories2007

    • Author(s)
      T. Sasao, M. Matsuura
    • Organizer
      DSD 2007, 10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools
    • Place of Presentation
      Lubeck, Germany
    • Related Report
      2009 Final Research Report
  • [Presentation] Design method of numerical function generators based on polynomial approximation for FPGA implementation2007

    • Author(s)
      S. Nagayama, T. Sasao, J.T. Butler
    • Organizer
      DSD 2007, 10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools
    • Place of Presentation
      Lubeck, Germany
    • Related Report
      2009 Final Research Report
  • [Presentation] Sum-of-generalized products expressions: Applications and minimization2007

    • Author(s)
      T. Sasao
    • Organizer
      IWLS-2007
    • Place of Presentation
      San Diego, California, U.S. A
    • Related Report
      2009 Final Research Report
  • [Presentation] Representations of elementary functions using edge-valued MDDs2007

    • Author(s)
      S. Nagayama, T. Sasao
    • Organizer
      ISMVL-2007
    • Place of Presentation
      Oslo, Norway
    • Related Report
      2009 Final Research Report
  • [Presentation] On designs of radix converters using arithmetic decompositions2007

    • Author(s)
      Y. Iguchi, T. Sasao, M. Matsuura
    • Organizer
      ISMVL-2007
    • Place of Presentation
      Oslo, Norway
    • Related Report
      2009 Final Research Report
  • [Presentation] An Application of 16-Valued logic to design of reconfigurable logic arrays2007

    • Author(s)
      T. Sasao
    • Organizer
      ISMVL-2007
    • Place of Presentation
      Oslo, Norway
    • Related Report
      2009 Final Research Report
  • [Presentation] Representations of elementary functions using edge-valued MDDs2007

    • Author(s)
      S.Nagayama and T.Sasao
    • Organizer
      ISMVL-2007
    • Place of Presentation
      Oslo,Norway
    • Related Report
      2007 Annual Research Report
  • [Presentation] On designs of radix converters using arithmetic decompositions2007

    • Author(s)
      Y.Iguchi, T.Sasao, and M.Matsuura
    • Organizer
      ISMVL-2007
    • Place of Presentation
      Oslo,Norway
    • Related Report
      2007 Annual Research Report
  • [Presentation] An Application of 16-Valued logic to design of reconfigurable logic arrays2007

    • Author(s)
      T.Sasao
    • Organizer
      ISMVL-2007
    • Place of Presentation
      Oslo,Norway
    • Related Report
      2007 Annual Research Report
  • [Presentation] The eigenfunction of the Reed-Muller transformation2007

    • Author(s)
      T.Sasao and J.T.Butler
    • Organizer
      RM-2007
    • Place of Presentation
      Oslo,Norway
    • Related Report
      2007 Annual Research Report
  • [Presentation] Sum-of-generalized products expressions:Applications and minimization2007

    • Author(s)
      T.Sasao
    • Organizer
      IWLS-2007
    • Place of Presentation
      San Diego,U.S.A
    • Related Report
      2007 Annual Research Report
  • [Presentation] An implementation of an address generator using hash memories2007

    • Author(s)
      T.Sasao and M.Matsuura
    • Organizer
      10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools
    • Place of Presentation
      Lubeck,Germany
    • Related Report
      2007 Annual Research Report
  • [Presentation] Design method of numerical function generators based on polynomial approximation for FPGA implementation2007

    • Author(s)
      S.Nagayama, T.Sasao, and J.T.Butler
    • Organizer
      10th EUROMICRO Coference on Digital System Design, Architectures, Methods and Tools
    • Place of Presentation
      Lubeck,Germany
    • Related Report
      2007 Annual Research Report
  • [Presentation] A hybrid logic simulator using LUT cascade emulators2007

    • Author(s)
      H.Nakahara, T.Sasao, and M.Matsuura
    • Organizer
      The 14th Workshop on Synthesis And System Integration of Mixed Information technologies
    • Place of Presentation
      Sapporo,Japan
    • Related Report
      2007 Annual Research Report
  • [Presentation] Implementations of reconfigurable logic arrays on FPGAs2007

    • Author(s)
      T.Sasao and H.Nakahara
    • Organizer
      International Conference on Field-Programmable Technology 2007
    • Place of Presentation
      Kitakyushu,Japan
    • Related Report
      2007 Annual Research Report
  • [Presentation] A hybrid logic simulator using LUT cascade emulators

    • Author(s)
      H. Nakahara, T. Sasao, M. Matsuura
    • Organizer
      The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007)
    • Place of Presentation
      Sapporo, Japan
    • Related Report
      2009 Final Research Report
  • [Book] Progress in Applications of Boolean Functions2010

    • Author(s)
      T.Sasao, J.T.Butler(ed)
    • Total Pages
      153
    • Publisher
      Morgan & Claypool Publishers
    • Related Report
      2009 Annual Research Report
  • [Book] Progress in Applications of Boolean Functions, Morgan & Claypool Publishers

    • Author(s)
      T. Sasao, J. T. Butler
    • Related Report
      2009 Final Research Report
  • [Remarks] ホームページ等

    • URL

      http://www.lsi-cad.com/sasao/index.html

    • Related Report
      2009 Final Research Report
  • [Remarks]

    • URL

      http://www.lsi-cad.com/sasao/index.html

    • Related Report
      2009 Annual Research Report
  • [Remarks]

    • URL

      http://www.lsi-cad.com/sasao/index.html

    • Related Report
      2008 Annual Research Report
  • [Remarks]

    • URL

      http://www.lsi-cad.com

    • Related Report
      2007 Annual Research Report

URL: 

Published: 2007-04-01   Modified: 2016-04-21  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi