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Memory-based VLSI brain research for realizing recognition, learning and decision capability

Research Project

Project/Area Number 19360163
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field Electron device/Electronic equipment
Research InstitutionHiroshima University

Principal Investigator

MATTAUSCH Hans j  Hiroshima University, ナノデバイス・バイオ融合科学研究所, 教授 (20291487)

Co-Investigator(Kenkyū-buntansha) KOIDE Tetsushi  広島大学, ナノデバイス・バイオ融合科学研究所, 准教授 (30243596)
Project Period (FY) 2007 – 2009
Project Status Completed (Fiscal Year 2009)
Budget Amount *help
¥17,940,000 (Direct Cost: ¥13,800,000、Indirect Cost: ¥4,140,000)
Fiscal Year 2009: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2008: ¥9,750,000 (Direct Cost: ¥7,500,000、Indirect Cost: ¥2,250,000)
Fiscal Year 2007: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Keywords連想メモリ / 知識システム / 知能情報処理 / 認識 / 学習と発見 / 判断 / VLSI / VLSIブレイン / 学習 / CMOS / アナログ回路
Research Abstract

Algorithms, architectures and integrated-circuits of functional-core units for an associative-memory-based VLSI brain were developed. Additionally, actual VLSI test-chips were designed and measured. A 180nm CMOS test chip of the "knowledge-pattern storage and nearest-distance search" unit achieved 50-245ns search time, <36.5mW power consumption and >99% positive detection rate. The developed algorithms and integrated circuits for realizing the "winner readout and recognition decision", "patterns learning" and "pattern optimization" units are based on the concepts of a recognition threshold, short/long term storage and reference-pattern updates derived from the previously recognized input patterns. We selected "handwritten character recognition" as a representative application for performance evaluation of the developed VLSI brain. With the reference-data-optimization algorithms, misclassification was reduced from 35% to 9%. A VLSI-brain test chip with automatic hand-written-character learning capability functioned correctly up to 100MHz, completed each reference-pattern learning and optimization step in about 2μs and had a low power consumption of 116mW.

Report

(4 results)
  • 2009 Annual Research Report   Final Research Report ( PDF )
  • 2008 Annual Research Report
  • 2007 Annual Research Report
  • Research Products

    (36 results)

All 2009 2008 2007

All Journal Article (6 results) (of which Peer Reviewed: 6 results) Presentation (22 results) Patent(Industrial Property Rights) (8 results) (of which Overseas: 1 results)

  • [Journal Article] Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture2009

    • Author(s)
      K. Okazaki, K. Awane, N. Nagaoka, T. Sugahara, T. Koide, H.J. Mattausch
    • Journal Title

      Jpn. J. Appl. Phys Vol.48,No.4

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture2009

    • Author(s)
      K.Okazaki
    • Journal Title

      Jpn.J.Appl.Phys. 48・4

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor2008

    • Author(s)
      T.Kumaki
    • Journal Title

      IEICE Trans.on Electronics 79-4

      Pages: 1409-1418

    • Related Report
      2008 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories2007

    • Author(s)
      M.A. Abedin, Y. Tanaka, A. Ahmadi, S. Sakakibara, T. Koide, H.J. Mattausch
    • Journal Title

      IEICE Trans. on Fundamentals vol.E90-A,No.6

      Pages: 1240-1243

    • NAID

      110007519195

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] Mixed Digital-Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search2007

    • Author(s)
      M. A. Abedin
    • Journal Title

      Jpn. J. Appl. Phys. 46・4B

      Pages: 2231-2237

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories2007

    • Author(s)
      M. A. Abedin
    • Journal Title

      IEICE Trans. on Fundamentals 90-A・6

      Pages: 1240-1243

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Presentation] 連想メモリベース適応学習LSIの応用とその評価2009

    • Author(s)
      川畑明雄
    • Organizer
      電子情報通信学会集積回路研究会議 (ICD2009-105)
    • Place of Presentation
      浜松市, 日本
    • Year and Date
      2009-12-14
    • Related Report
      2009 Annual Research Report
  • [Presentation] Associative- Memory-Based Prototype LSI with Recognition and On-line Learning Capability and its Application to Handwritten Characters2009

    • Author(s)
      W. Imafuku, S. Sakakibara, A. Kawabata, T. Ansari, H.J. Mattausch, T. Koide
    • Organizer
      Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS'2009)
    • Place of Presentation
      Kanazawa, Japan
    • Year and Date
      2009-12-09
    • Related Report
      2009 Final Research Report
  • [Presentation] Associative-Memory-Based Prototype LSI with Recognition and On-line Learning Capability and its Application to Handwritten Characters2009

    • Author(s)
      W.Imafuku
    • Organizer
      International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS'2009)
    • Place of Presentation
      Kanazawa, Japan
    • Year and Date
      2009-12-09
    • Related Report
      2009 Annual Research Report
  • [Presentation] VLSI-Architecture for Enabling Multiple Parallel Associative Searches with Standard SRAM Macros2009

    • Author(s)
      T. Kumaki, Y. Imai, T. Koide, H.J. Mattausch
    • Organizer
      Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS'2009)
    • Place of Presentation
      Kanazawa, Japan
    • Year and Date
      2009-12-07
    • Related Report
      2009 Final Research Report
  • [Presentation] VLSI-Architecture for Enabling Multiple Parallel Associative Searches with Standard SRAM Macros2009

    • Author(s)
      熊木武志
    • Organizer
      International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS'2009)
    • Place of Presentation
      Kanazawa, Japan
    • Year and Date
      2009-12-07
    • Related Report
      2009 Annual Research Report
  • [Presentation] 画像圧縮コードブックを最適にする連想メモリベース自動学習の研究2009

    • Author(s)
      川畑明雄
    • Organizer
      第11回IEEE広島支部学生シンポジウム
    • Place of Presentation
      山口市, 日本
    • Year and Date
      2009-11-21
    • Related Report
      2009 Annual Research Report
  • [Presentation] High-Speed Face Detection in Images with Massive-Parallel Bit-Serial SIMD Processor Using Haar-Like Features2009

    • Author(s)
      Y.Imai
    • Organizer
      2009 International Conference on Solid State Devices and Materials (SSDM'2009)
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2009-10-08
    • Related Report
      2009 Annual Research Report
  • [Presentation] 3値多ポート連想メモリの開発とその応用例2009

    • Author(s)
      熊木武志
    • Organizer
      電子情報通信学会回路とシステム研究会議(CAS2009-36)
    • Place of Presentation
      広島市, 日本
    • Year and Date
      2009-09-25
    • Related Report
      2009 Annual Research Report
  • [Presentation] 連想メモリベース自動学習LSI アーキテクチャと手書き文字認識への適用2009

    • Author(s)
      今福渉
    • Organizer
      電子情報通信学会 回路とシステム研究会議(CAS2009-36)
    • Place of Presentation
      広島市, 日本
    • Year and Date
      2009-09-25
    • Related Report
      2009 Annual Research Report
  • [Presentation] VLSI Design of a Handwritten-Character Learning and Recognition system based on Associative Memory2009

    • Author(s)
      S. Sakakibara, W. Imafuku, A. Kawabata, T. Ansari, H.J. Mattausch, T. Koide
    • Organizer
      15th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2009)
    • Place of Presentation
      Okinawa, Japan
    • Year and Date
      2009-03-09
    • Related Report
      2009 Final Research Report
  • [Presentation] VLSI Design of a Handwritten-Character Learning and Recognition system based on Associative Memory2009

    • Author(s)
      S.Sakakibara
    • Organizer
      15th Workshop on Synthesis and System Integration of Mixed Information Technologies(SASIMI'2009)
    • Place of Presentation
      Okinawa, Japan
    • Year and Date
      2009-03-09
    • Related Report
      2008 Annual Research Report
  • [Presentation] Grouping Method based on Feature Matching for Tracking and Recognition of Complex Objects2009

    • Author(s)
      N. Nagaoka, K. Okazaki, T. Sugahara, T. Koide, H.J. Mattausch
    • Organizer
      Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS'2008)
    • Place of Presentation
      Bangkok, , Thailand
    • Year and Date
      2009-02-09
    • Related Report
      2009 Final Research Report
  • [Presentation] Grouping Method based on Feature Matching for Tracking and Recognition of Complex Objects2009

    • Author(s)
      N.Nagaoka
    • Organizer
      International Symposium on Intelligent Signal Processing and Communication Systems(ISPACS'2008)
    • Place of Presentation
      Bangkok, Thailand
    • Year and Date
      2009-02-09
    • Related Report
      2008 Annual Research Report
  • [Presentation] Hardware Realization of Two-Stage Pattern Matching System using Fully-Parallel Associative Memories2008

    • Author(s)
      M.A.Abedin
    • Organizer
      5^<th> International Conference on Electrical and Computer Engineering(ICECE'2008)
    • Place of Presentation
      Dhaka, Bangladesh
    • Year and Date
      2008-12-20
    • Related Report
      2008 Annual Research Report
  • [Presentation] 領域成長型画像分割アルゴリズムを用いた画像分割の精度改善2008

    • Author(s)
      菅原達也
    • Organizer
      平成20年度電気・情報関連学会中国支部第59回連合大会
    • Place of Presentation
      山口市, 日本
    • Year and Date
      2008-10-24
    • Related Report
      2008 Annual Research Report
  • [Presentation] スケーリングによる連想メモリの性能向上とばらつき影響の評価2008

    • Author(s)
      今福渉
    • Organizer
      平成20年度電気・情報関連学会中国支部第59回連合大会
    • Place of Presentation
      山口市, 日本
    • Year and Date
      2008-10-24
    • Related Report
      2008 Annual Research Report
  • [Presentation] 学習機能を実現する連想メモリのLSI設計2007

    • Author(s)
      榊原 尚吾
    • Organizer
      平成19年度 電気・情報関連学会中国支部第58回連合大会
    • Place of Presentation
      広島,日本
    • Year and Date
      2007-10-20
    • Related Report
      2007 Annual Research Report
  • [Presentation] Associative Memory Design Realizing Reference-Pattern Recognition and Learning based on Short/Long-Term Storage Concept2007

    • Author(s)
      S. Sakakibara
    • Organizer
      14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2007)
    • Place of Presentation
      Sapporo, Japan
    • Year and Date
      2007-10-15
    • Related Report
      2007 Annual Research Report
  • [Presentation] Hardware Realization of Two-Stage Pattern Matching System using Fully-Parallel Associative Memories2007

    • Author(s)
      M. A. Abedin
    • Organizer
      14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2007)
    • Place of Presentation
      Sapporo, Japan
    • Year and Date
      2007-10-15
    • Related Report
      2007 Annual Research Report
  • [Presentation] Area Efficient Fully Parallel Associative Memory with Fast Winner Search Capability2007

    • Author(s)
      Y. Tanaka
    • Organizer
      14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2007)
    • Place of Presentation
      Sapporo, Japan
    • Year and Date
      2007-10-15
    • Related Report
      2007 Annual Research Report
  • [Presentation] Developing a Reliable Learning Model for Cognitive Classification Tasks Using an Associative Memory2007

    • Author(s)
      Ahmadi, H.J. Mattausch, M.A. Abedin, T. Koide, Y. Shirakawa, M.A. Ritonga
    • Organizer
      Proceedings of the 2007 IEEE Symposium on Computational Intelligence in Image and Signal Processing (CIISP'2007)
    • Place of Presentation
      Honolulu, USA
    • Year and Date
      2007-04-03
    • Related Report
      2009 Final Research Report
  • [Presentation] Developing a Reliable Learning Model for Cognitive Classification Tasks Using an Associative Memory2007

    • Author(s)
      H. J. Mattausch
    • Organizer
      2007 IEEE Symposium on Computational Intelligence in Image and Signal Processing (CIISP'2007)
    • Place of Presentation
      Honolulu, USA
    • Year and Date
      2007-04-03
    • Related Report
      2007 Annual Research Report
  • [Patent(Industrial Property Rights)] 連想メモリ2009

    • Inventor(s)
      H.J.Mattausch, T.Koide, 他
    • Industrial Property Rights Holder
      広島大学
    • Filing Date
      2009-10-01
    • Related Report
      2009 Final Research Report
  • [Patent(Industrial Property Rights)] 連想メモリおよびそれを用いた検索システム2009

    • Inventor(s)
      T.Koide, H.J.Mattausch, 他
    • Industrial Property Rights Holder
      広島大学
    • Acquisition Date
      2009-08-12
    • Related Report
      2009 Final Research Report
  • [Patent(Industrial Property Rights)] 連想メモリ2009

    • Inventor(s)
      H. J. Mattausch
    • Industrial Property Rights Holder
      広島大学
    • Filing Date
      2009-10-01
    • Related Report
      2009 Annual Research Report
  • [Patent(Industrial Property Rights)] 連想メモリおよびそれを用いた検索システム2009

    • Inventor(s)
      T. Koide
    • Industrial Property Rights Holder
      広島大学
    • Filing Date
      2009-08-12
    • Related Report
      2009 Annual Research Report
  • [Patent(Industrial Property Rights)] 連想メモリ2008

    • Inventor(s)
      T.Koide
    • Industrial Property Rights Holder
      広島大学
    • Filing Date
      2008-04-07
    • Related Report
      2008 Annual Research Report
  • [Patent(Industrial Property Rights)] オフセット除去回路、それを備えた連想メモリおよびオフセット電圧の除去方法2008

    • Inventor(s)
      H.J.Mattausch
    • Industrial Property Rights Holder
      広島大学
    • Filing Date
      2008-07-31
    • Related Report
      2008 Annual Research Report
  • [Patent(Industrial Property Rights)] 増幅回路および連想メモリ2008

    • Inventor(s)
      H.J. Mattausch
    • Industrial Property Rights Holder
      広島大学学長
    • Filing Date
      2008-02-25
    • Related Report
      2007 Annual Research Report
    • Overseas
  • [Patent(Industrial Property Rights)] 連想メモリおよびそれを用いた検索システム2007

    • Inventor(s)
      アベディンモハマドアノワルル
    • Industrial Property Rights Holder
      広島大学学長
    • Filing Date
      2007-11-30
    • Related Report
      2007 Annual Research Report

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Published: 2007-04-01   Modified: 2016-04-21  

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