| Project/Area Number |
19360163
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Hiroshima University |
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Principal Investigator |
MATTAUSCH Hans j Hiroshima University, ナノデバイス・バイオ融合科学研究所, 教授 (20291487)
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| Co-Investigator(Kenkyū-buntansha) |
KOIDE Tetsushi 広島大学, ナノデバイス・バイオ融合科学研究所, 准教授 (30243596)
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| Project Period (FY) |
2007 – 2009
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| Project Status |
Completed (Fiscal Year 2009)
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| Budget Amount *help |
¥17,940,000 (Direct Cost: ¥13,800,000、Indirect Cost: ¥4,140,000)
Fiscal Year 2009: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2008: ¥9,750,000 (Direct Cost: ¥7,500,000、Indirect Cost: ¥2,250,000)
Fiscal Year 2007: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
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| Keywords | 連想メモリ / 知識システム / 知能情報処理 / 認識 / 学習と発見 / 判断 / VLSI / VLSIブレイン / 学習 / CMOS / アナログ回路 |
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| Research Abstract |
Algorithms, architectures and integrated-circuits of functional-core units for an associative-memory-based VLSI brain were developed. Additionally, actual VLSI test-chips were designed and measured. A 180nm CMOS test chip of the "knowledge-pattern storage and nearest-distance search" unit achieved 50-245ns search time, <36.5mW power consumption and >99% positive detection rate. The developed algorithms and integrated circuits for realizing the "winner readout and recognition decision", "patterns learning" and "pattern optimization" units are based on the concepts of a recognition threshold, short/long term storage and reference-pattern updates derived from the previously recognized input patterns. We selected "handwritten character recognition" as a representative application for performance evaluation of the developed VLSI brain. With the reference-data-optimization algorithms, misclassification was reduced from 35% to 9%. A VLSI-brain test chip with automatic hand-written-character learning capability functioned correctly up to 100MHz, completed each reference-pattern learning and optimization step in about 2μs and had a low power consumption of 116mW.
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