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Research on High Dependable Test for Crosstalk Faults in High Speed VLSIs

Research Project

Project/Area Number 19500045
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionEhime University

Principal Investigator

HIGAMI Yoshinobu  Ehime University, 大学院・理工学研究科, 准教授 (40304654)

Co-Investigator(Kenkyū-buntansha) TAKAHASHI Hiroshi  愛媛大学, 大学院・理工学研究科, 准教授 (80226878)
Project Period (FY) 2007 – 2009
Project Status Completed (Fiscal Year 2009)
Budget Amount *help
¥3,380,000 (Direct Cost: ¥2,600,000、Indirect Cost: ¥780,000)
Fiscal Year 2009: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2008: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2007: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
KeywordsVLSI(大規模集積回路) / テスト / 故障診断 / クロストーク故障 / テストパターン生成 / トランジスタショート / ゲートレベルツール / 故障シミュレーション / 高信頼化 / 論理回路 / VLSIのテスト / シミュレーション / 故障モデル
Research Abstract

In this research, a testing method for crosstalk faults in VLSI (Very Large Scaled Integrated Circuit) circuits has been proposed. A crosstalk fault is induced by coupling interaction between neighbor two lines, and it is hard to detect by the testing method for conventional fault models. We analyzed the fault behavior of crosstalk faults to define a fault model, and proposed a test generation method. Moreover we enhanced the method for transistor shorts to improve fault diagnosis and test pattern generation.

Report

(4 results)
  • 2009 Annual Research Report   Final Research Report ( PDF )
  • 2008 Annual Research Report
  • 2007 Annual Research Report
  • Research Products

    (8 results)

All 2009 2008

All Journal Article (4 results) (of which Peer Reviewed: 2 results) Presentation (4 results)

  • [Journal Article] An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation2009

    • Author(s)
      Y. Higami, K.K. Saluja, H. Takahashi, S. Kobayashi, Y. Takamatsu
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology vol.2(in press)

      Pages: 250-262

    • NAID

      130000140280

    • Related Report
      2009 Final Research Report
  • [Journal Article] Addressing Defect Coverage through Generating Test Vectors for Transistor Defects2009

    • Author(s)
      Y. Higami, K.K. Saluja, H. Takahashi, S. Kobayashi, Y. Takamatsu
    • Journal Title

      IEICE Trans. Fundamentals vol.E92-A,no.12

      Pages: 3506-3513

    • NAID

      10026861532

    • Related Report
      2009 Final Research Report
  • [Journal Article] An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation2009

    • Author(s)
      Y.Higami, K.K.Saluja, H.Takahashi, S.Kobayashi, Y.Takamatsu
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology 2

      Pages: 250-262

    • NAID

      130000140280

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Addressing Defect Coverage through Generating Test Vectors for Transistor Defects2009

    • Author(s)
      Y.Higami, K.K.Saluja, H.Takahashi, S.Kobayashi, Y.Takamatsu
    • Journal Title

      IEICE Trans.Fundamentals E92-A

      Pages: 3505-3513

    • NAID

      10026861532

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Presentation] Increasing Defect Coverage by Generating Test Vectors for Stuck-open Faults2008

    • Author(s)
      Y. Higami, K.K. Saluja, H. Takahashi, K. Kobayashi, Y. Takamatsu
    • Organizer
      Proc. IEEE Seventeenth Asian Test Symposium
    • Year and Date
      2008-11-26
    • Related Report
      2009 Final Research Report
  • [Presentation] Increasing Defect Coverage by Generating Test Vectors for Stuck-open Faults2008

    • Author(s)
      Y. Higami, K. K. Saluja, H. Takahasi, K. Kobayashi, Y. Takamatsu
    • Organizer
      アジアテストシンポジウム
    • Place of Presentation
      札幌
    • Year and Date
      2008-11-25
    • Related Report
      2008 Annual Research Report
  • [Presentation] スキャン回路におけるクロストーク故障の検出可能性について2008

    • Author(s)
      樋上喜信, 高橋寛, 廣瀬雅人, 小林真也, 高松雄三
    • Organizer
      子情報通信学会総合大会
    • Year and Date
      2008-03-18
    • Related Report
      2009 Final Research Report
  • [Presentation] スキャン回路におけるクロストーク故障の検出可能性について2008

    • Author(s)
      樋上 喜信, 高橋 寛, 廣瀬 雅人, 小林 真也, 高松 雄三
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      早稲田大学(北九州市)
    • Year and Date
      2008-03-18
    • Related Report
      2007 Annual Research Report

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Published: 2007-04-01   Modified: 2016-04-21  

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