VLSI CIRCUIT DESIGNS with SOFT ERROR TOLERANCE
| Project/Area Number |
19560335
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Chiba University |
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Principal Investigator |
ITO Hideo Chiba University, 大学院・融合科学研究科, 教授 (90042647)
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| Co-Investigator(Kenkyū-buntansha) |
NAMBA Kazuteru 千葉大学, 大学院・融合科学研究科, 助教 (60359594)
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| Project Period (FY) |
2007 – 2009
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| Project Status |
Completed (Fiscal Year 2009)
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| Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2009: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2008: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2007: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Keywords | 回路設計 / CAD / ソフトエラー / VLSI / ラッチ / スキャン設計 / テスト容易化設計 / 遅延故障 / テスト容易化 / シグナルインテグリティ / 2線式論理 / FPGA / スキャンFF |
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| Research Abstract |
Soft errors (SEs) are radiation-induced transition pulses caused by neutrons from cosmic rays or alpha particles from packaging material. This research got the two type results of (a) VLSI circuit design with the property of SE tolerance, and (b) test generation and easily testable design for SE tolerant circuits. In (a), circuit design masking SE pulses caused in combinational circuit parts, and circuit designs for SE hardened latch or flip-flop have been proposed. In (b), easily testable scan structure for delay faults with the property of SE tolerance has been proposed.
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Report
(4 results)
Research Products
(32 results)
