A studay for SRAM Terminal Biasing Scheme for Ultra-Low Operating Voltage Applications for NanoMeter Era

• Project/Area Number: 19560363
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Fukuoka Institute of Technology
• Principal Investigator: YAMAUCHI Hiroyuki Fukuoka Institute of Technology, 情報工学部, 教授 (70425239)
• Project Period (FY): 2007 – 2008
• Project Status: Completed (Fiscal Year 2008)
• Budget Amount: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000); Fiscal Year 2008: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000); Fiscal Year 2007: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
• Keywords: SRAM / SRAMスケーリング / スタティックノイズマージン / ライトマージン / マージンアシスト回路 / EOTのスケーリング / σVtのスケーリング / セルトポロジー

Research Abstract

SRAMのサイズスケーリングのベースに影響を与える可能性のあるSRAMセルトポロジーとマージンアイッスト方式の技術について調査し、スケーリングのペースに与える影響を定量的に求め、45nm以降15nm迄のプロセススケーリングを考慮した各種アシスト回路のマージンアシスト回路方式の予測を行い、最もサイズスケーリングのペースを速くできるSRAMセルトポロジーとマージンアシスト回路を明らかにした。

Research Products

• [Journal Article] A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies (2009)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEEE Transaction on VLSI Systems
  • Peer Reviewed
• [Journal Article] A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era (2009)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEEK Journal of Semiconductor Technology and Science 9-1 Pages: 37-50
  • Peer Reviewed
• [Journal Article] A 0.6 V Dual-Rail Compiler SRAM Design on 45nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs (2009)
  • Author(s): Yen Huei Chen, Gary Chan, Shao Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Robin Lee, H. J. Liao, and Hiroyuki Yamauchi
  • Journal Title: IEEE Journal of Solid State Circuits 44-4 Pages: 1209-1215
  • Peer Reviewed
• [Journal Article] A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies (2009)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEEE Transaction on VLSI Systems (掲載確定)
  • Peer Reviewed
• [Journal Article] A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era (2009)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEEK JOURNAL OF SEMICONDUCTOR TECHNOLOY AND SCIENCE Vol. 9, No. 1 Pages: 37-50
  • Peer Reviewed
• [Journal Article] A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs (2009)
  • Author(s): Yen Huei Chen, Gary Chan, Shao Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Robin Lee, H. J. Liao, Hiroyuki Yamauchi
  • Journal Title: IEEE Journal of Solid state Circuits vol. 44, No. 4 Pages: 1209-1215
  • Peer Reviewed
• [Journal Article] A stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses (2008)
  • Author(s): Toshikazu Suzuki, Hiroyuki YAMAUCHI, Yoshinobu Yamagami, Katsuji Satomi and Hironori Akamatsu
  • Journal Title: IEEE Journal of Solid State Circuits 43 Pages: 2109-2119
  • Peer Reviewed
• [Journal Article] A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses (2008)
  • Author(s): Toshikazu Suzuki, Hiroyuki YAMAUCHI, Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu
  • Journal Title: IEEE Journal of Solid state Circuits Vol. 43 Pages: 2109-2119
  • Peer Reviewed
• [Journal Article] Embedded SRAM Trend in Nano-Scale CMOS (2008)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEEE MTDT 2007 Proceeding(Dec, 2007) Pages: 19-22
  • Peer Reviewed
• [Journal Article] An embedded SRAM and its Scaling trend (2008)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEEE ISSCC2008, Advanced Circuit Memory Forum "Embedded memory"(Feb, 2008)
  • Peer Reviewed
• [Journal Article] A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving Against Simultaneous Read/Write Disturbed Accesses (2007)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEICE Transactions on Electronics E90-C-4 Pages: 749-757
  • NAID: 110007522174
  • Peer Reviewed
• [Journal Article] A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-volatile Memory Cell Design with a Differential Cell Architecture in a 110nm Pure CMOS Logic Process for a System LSI (2007)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEICE Transactions on Electronics E90-C-5 Pages: 1129-1137
  • Peer Reviewed
• [Journal Article] A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Cheme (2007)
  • Author(s): Suzuki T, Yamauchi H, Satomi K, Akamatsu H
  • Journal Title: Custom Integrated Circuits Conference, 2007. CICC apos ; 07. IEEE Volume Issue Pages: 233-236
  • Peer Reviewed
• [Journal Article] A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving Against Simultaneous Read/Write Disturbed Accesses (2007)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEICE Transactions on Electronics.(Vol.E90-C, No.4, April, 2007) Vol.E90-C Pages: 749-757
  • NAID: 110007522174
  • Peer Reviewed
• [Journal Article] A PND(PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-volatile Memory Cell Design with a Differential Cell Architecture in a 110nm Pure CMOS Logic Process for a System LSI (2007)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEICE Transactions on Electronics.(Vol.E90-C, No.5, May, 2007, pp.1129-1137) Vol.E90-C Pages: 1129-1137
  • Peer Reviewed
• [Journal Article] A Stable SRAM Mitigating Cell-Margin Asymmetry with A Disturb-Free Biasing Scheme (2007)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEEE Custom Integrated Circuits Conference Proceedings (2007, Sept.16-19) Pages: 233-236
  • Peer Reviewed
• [Journal Article] Embedded SRAM Circuit Technologies for a 45nm and beyond (2007)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: International Conference on ASIC EIectronic Version Proceedings
  • Peer Reviewed
• [Journal Article] A 45nm Dual-Port SRAM with Write and Read Capability Enhancement at Low Voltage (2007)
  • Author(s): Hiroyuki Yamauchi
  • Journal Title: IEEE International System on Chip Conference, (Sept.26-29 2007) Pages: 211-214
  • Peer Reviewed
• [Presentation] Variation-Tolerant SRAM Circuit Design (2009)
  • Author(s): Hiroyuki Yamauchi
  • Organizer: IEEE ISSCC 2009 Tutorial
  • Place of Presentation: San Francisco USA (MARRIOTT HOTEL)
• [Presentation] Variation-Tolerant SRAM Circuit Design (2009)
  • Author(s): Hiroyuki Yamauchi
  • Organizer: IEEE ISSCC 2009
  • Place of Presentation: San Francisco USA MARRIOTT HOTEL
• [Presentation] A discussion on SRAM Circuit Design Trend in Deeper Nano-meter Era (2008)
  • Author(s): Hiroyuki Yamauchi
  • Organizer: International SoC Conference ISOCC 2008
  • Place of Presentation: 韓国・釜山 (BEXCO Convention Halls)
  • Year and Date: 2008-11-25
• [Presentation] A Discussion on SRAM Circuit Design Trend in Deeper Nano-meter Era (2008)
  • Author(s): Hiroyuki Yamauchi
  • Organizer: International SoC Conference IS0CC2008
  • Place of Presentation: 韓国釜山BEXCO Convention Halls
  • Year and Date: 2008-11-25
• [Presentation] SRAMの党閾値電圧ばらつきによる書き込みマージンへの影響に関する研究 (2008)
  • Author(s): 貞方健太・山内寛行・山野辺泰治
  • Organizer: 電気学会九州支部連合大会
  • Place of Presentation: 大分大学
  • Year and Date: 2008-09-24
• [Presentation] ソース同相・差動制御によるWRM改善効果のためのDC解析とトランジェント解析による比較検討 (2008)
  • Author(s): 山野辺泰治・貞方健太・山内寛行
  • Organizer: 電気学会九州支部連合大会
  • Place of Presentation: 大分大学
  • Year and Date: 2008-09-24
• [Presentation] DC解析とTransient解析によるSRAMの動作Marginの比較検討 (2008)
  • Author(s): 横尾章一郎・山内寛行
  • Organizer: 電気学会九州支部連合大会
  • Place of Presentation: 大分大学
  • Year and Date: 2008-09-24
• [Presentation] SRAMの閾値電圧ばらつきによる書き込みマージンへの影響に関する研究 (2008)
  • Author(s): 貞方健太, 山内寛行, 山野辺泰治
  • Organizer: 電気学会九州支部連合大会
  • Place of Presentation: 大分大学
  • Year and Date: 2008-09-24
• [Presentation] 半導体設計支援ソフトウェアの開発 (2008)
  • Author(s): 齊藤真, 山内寛行
  • Organizer: 電気学会九州支部連合大会
  • Place of Presentation: 大分大学
  • Year and Date: 2008-09-24
• [Presentation] C-12-28SRAM同相・差動ソース電位制御の書き込みマージンの比較検討 (2008)
  • Author(s): 山野辺 泰治、山内 寛行
  • Organizer: 電子情報通信学会全国大会
  • Place of Presentation: 北九州大学
  • Year and Date: 2008-03-19
• [Presentation] An embedded SRAM and its Scaling trend (2008)
  • Author(s): Hiroyuki Yamauchi
  • Organizer: IEEE ISSCC2008, Advanced Circuit Memory Forum "Embedded memory"
  • Place of Presentation: San Francisco
  • Year and Date: 2008-02-03
• [Presentation] A 0.6V 45nm Adaptive Dual-rail SRAM Compiler Circuit Design for Lower VDD_min VLSIs (2008)
  • Author(s): Y.H. Chen, W.M. Chan, S.Y. Chou, H.J. Liao, H.Y. Pan, J.J. Wu, C.H. Lee, S.M. Yang, Y.C. Liu, Hiroyuki Ymauchi
  • Organizer: IEEE symposium on VLSI Circuit 2008
  • Place of Presentation: Honolulu Hawaii USA (Hilton Hawaiian Village)
• [Presentation] A 0.6V 45nm Adaptive Dual-rail SRAM Compiler Circuit Design for Lower VDD_min VLSIs (2008)
  • Author(s): Y. H. Chen, W. M. Chan, S. Y. Chou, H. J. Liao, H. Y. Pan, J. J. Wu, C. H. Lee, S. M. Yang, Y. C. Liu, TSMC, Taiwan, Hiroyuki Yamauchi
  • Organizer: IEEE Symposium on VLSI Circuit
  • Place of Presentation: Honolulu Hawaii USA Hilton Hawaiian Village
• [Presentation] Embedded SRAM Trend in Nano-Scale CMOS (2007)
  • Author(s): Hiroyuki Yamauchi
  • Organizer: IEEE MTDT 2007Proceeding
  • Place of Presentation: Taipei (Taiwan)
  • Year and Date: 2007-12-04
• [Presentation] Embedded SRAM Circuit Technologies for a 45 nm and beyond (2007)
  • Author(s): Hiroyuki Yamauchi
  • Organizer: International Conference on ASIC Electronic Version Proceedings
  • Place of Presentation: Guilin (China)
  • Year and Date: 2007-10-28
• [Presentation] A 45nm Dual-Port SRAM with Write and Read Capability Enhancement at Low Voltage (2007)
  • Author(s): Hiroyuki Yamauchi
  • Organizer: IEEE International System on Chip Conference
  • Place of Presentation: Busan (Korea)
• [Book] Embedded Memories for Nano-Scale VLSIs (2009)
  • Author(s): Hiroyuki Yamauchi
• [Book] 電子ジャーナル、2009半導体テクノロジー大全 (2009)
  • Author(s): 山内寛行
• [Book] Embedded Memories for Nano-Scale VLSIs (2009)
  • Author(s): Hiroyuki Yamauchi
  • Total Pages: 400
  • Publisher: Springer
• [Book] 2009半導体テクノロジー大全 (2009)
  • Author(s): 山内寛行
  • Total Pages: 650
  • Publisher: 電子ジャーナル
• [Remarks]
  • URL: http://www.fit.ac.jp/~yamauchi/
• [Remarks]
  • URL: http://www.fit.ac.jp/~yamauchi/