Low-Power High-Performance VLSI design using 1-out-of-4 code

• Project/Area Number: 19700039
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: The University of Tokyo
• Principal Investigator: IMAI Masashi The University of Tokyo, 駒場オープンラボラトリー, 特任准教授 (70323665)
• Project Period (FY): 2007 – 2008
• Project Status: Completed (Fiscal Year 2008)
• Budget Amount: ¥3,600,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥300,000); Fiscal Year 2008: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000); Fiscal Year 2007: ¥2,300,000 (Direct Cost: ¥2,300,000)
• Keywords: 計算機システム / 半導体超微細化 / 低消費電力 / 遅延変動 / 非同期式回路

Research Abstract

半導体製造技術の微細化やシステムの大規模化に伴う消費電力問題・遅延変動問題に対して、信号遷移数の少ない1-out-of-4符号を用いた非同期式回路理論に基づくVLSI設計方式、m-out-of-n符号を用いた非同期式回路における複数閾値電圧トランジスタを用いた回路非動作時の漏れ電流削減手法を提案し、実チップ設計を通した評価により、遅延変動に対する耐性が高く、消費電力が小さくかつ高性能なVLSIを実現できることを確認した。

Research Products

• [Presentation] Fine-grain leakage power reduction method for m-out-o-f-n encoded circuits using multi-threshold-voltage transistors (2009)
  • Author(s): Masashi Imai, Kouei Takada, Takashi Nanya
  • Organizer: ASYNC2009 (accepted)
  • Place of Presentation: North Carolina, USA
  • Year and Date: 2009-05-20
• [Presentation] Fine-grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-Threshold-Voltage Transistors (2009)
  • Author(s): Masashi Imai, Kouei Takada, Takashi Nanya
  • Organizer: Proc Async2009
  • Place of Presentation: Chapel Hill, NC, USA
• [Presentation] マルチ閾値電圧トランジスタを用いた2線2相式非同期式回路のリーク電力削減手法 (2008)
  • Author(s): 高田幸永, 今井雅, 南谷崇
  • Organizer: デザインガイア
  • Place of Presentation: 北九州学園研究都市
  • Year and Date: 2008-11-19
• [Presentation] A Design Method for 1-out-of-4 Encoded Low-Power Self-Timed Circuits using Standard Cell Libraries (2008)
  • Author(s): Masashi Imai, Takashi Nanya
  • Organizer: 8th International Conference on Application of Concurrency to System Design 2008 (to appear)
  • Place of Presentation: Xi'an, China
  • Year and Date: 2008-06-25
• [Presentation] マルチ閾値電圧トランジスタを用いた2線2相式非同期式回路のリーク電力削減手法 (2008)
  • Author(s): 高田幸永,今井雅,中村宏,南谷崇
  • Organizer: 電子情報通信学会技術研究報告
  • Place of Presentation: 北九州
• [Presentation] Performance Comparison between Self-timed Circuits and Synchronous Circuits Based on the Technology Roadmap of Semiconductors (2008)
  • Author(s): Masashi Imai, Takashi Nanya
  • Organizer: Proc. DSN08 2nd Workshop on Dependable and Secure Nanocomputing, Supplemental Proceedings
  • Place of Presentation: Anchorage, USA
• [Presentation] A Design Method for 1-out-of-4 Encoded Low-Power Self-Timed Circuits using Standard Cell Libraries (2008)
  • Author(s): Masashi Imai, Takashi Nanya
  • Organizer: Proc. ACSD08
  • Place of Presentation: Xi-an, China