Behavioral Synthesis of High-Performance LSIs from Large Sequential Programs

• Project/Area Number: 19700040
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: Nagoya University
• Principal Investigator: TOMIYAMA Hiroyuki Nagoya University, 大学院・情報科学研究科, 准教授 (80362292)
• Project Period (FY): 2007 – 2009
• Project Status: Completed (Fiscal Year 2009)
• Budget Amount: ¥3,760,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥660,000); Fiscal Year 2009: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000); Fiscal Year 2008: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000); Fiscal Year 2007: ¥900,000 (Direct Cost: ¥900,000)
• Keywords: 動作合成 / 高位合成 / 設計自動化 / システムオンチップ / 集積回路

Research Abstract

We have developed behavioral synthesis technologies which automatically generate high-performance LSIs (large scale integrated circuits) from large sequential programs. While traditional methods generate a single huge module from a large sequential program, our methods generate multiple small modules in such a way that overall datapath area is minimized and course- and fine-grained parallelisms are fully exploited.

Research Products

• [Journal Article] Partitioning of Behavioral Descriptions Exploiting Function-Level Parallelism (2010)
  • Author(s): Y. Hara, H. Tomiyama, S. Honda, H. Takada
  • Journal Title: IEICE Trans. Fundamentals vol.E93-A,no.2 Pages: 488-499
  • NAID: 110006824843
  • Peer Reviewed
• [Journal Article] Partitioning of Behavioral Descriptions Exploiting Function-Level Parallelism (2010)
  • Author(s): Y.Hara, H.Tomiyama, S.Honda, H.Takada
  • Journal Title: IEICE Trans.Fundamentals E93-A(2) Pages: 488-499
  • NAID: 110006824843
  • Peer Reviewed
• [Journal Article] Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-Based High-Level Synthesis (2009)
  • Author(s): Y. Hara, H. Tomiyama, S. Honda, H. Takada
  • Journal Title: IPSJ Journal of Information Processing (JIP) vol.17 Pages: 242-254
  • NAID: 40019547220
  • Peer Reviewed
• [Journal Article] Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-Based High-Level Synthesis (2009)
  • Author(s): Y.Hara, H.Tomiyama, S.Honda, H.Takada
  • Journal Title: Journal of Iformation Processing (JIP) 17 Pages: 242-254
  • NAID: 40019547220
  • Peer Reviewed
• [Journal Article] High-Level Synthesis of Software Function Calls (2008)
  • Author(s): M. Nishimura, N. Ishiura, Y. Ishimori, H. Kanbara, H. Tomiyama
  • Journal Title: IEICE Trans. Fundamentals vol.E91-A,no.12 Pages: 3556-3558
  • NAID: 10026853994
  • Peer Reviewed
• [Journal Article] Embedded System Covalidation with RTOS Model and FPGA (2008)
  • Author(s): S. Shibata, S. Honda, Y. Hara, H. Tomiyama, H. Takada
  • Journal Title: IPSJ Trans. System LSI Design Methodology (TSLDM) vol.1 Pages: 126-130
  • NAID: 130002073187
  • Peer Reviewed
• [Journal Article] Embedded System Covalidation with RTOS Model and FPGA (2008)
  • Author(s): Seiya Shibata
  • Journal Title: IPSJ Trans. System LSI Design Methodology 1 Pages: 126-130
  • Peer Reviewed
• [Journal Article] High-Level Synthesis of Software Function Calls (2008)
  • Author(s): Masanari Nishimura
  • Journal Title: IEICE Trans. Fundamentals E91-A Pages: 3556-3558
  • Peer Reviewed
• [Journal Article] Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis (2007)
  • Author(s): Y. Hara, H. Tomiyama, S. Honda, H. Takada, K. Ishii
  • Journal Title: IEICE Trans. Fundamentals vol.E90-A,no.12 Pages: 2853-2862
  • NAID: 110007538032
  • Peer Reviewed
• [Journal Article] Function Call Optimization for Efficient Behavioral Synthesis (2007)
  • Author(s): Y. Hara, H. Tomiyama, S. Honda, H. Takada
  • Journal Title: IEICE Trans. Fundamentals vol.E90-A,no.9 Pages: 2032-2036
  • NAID: 110007538120
  • Peer Reviewed
• [Journal Article] Function Call Optimization for Efficient Behavioral Synthesis (2007)
  • Author(s): Yuko Hara
  • Journal Title: IEICE Trans. Fundamentals E90-A・9 Pages: 2032-2036
  • Peer Reviewed
• [Journal Article] Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis (2007)
  • Author(s): Yuko Hara
  • Journal Title: IEICE Trans. Fundamentals E90-A・12 Pages: 2853-2862
  • Peer Reviewed
• [Presentation] Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis (2010)
  • Author(s): T. Matsuba, Y. Hara, H. Tomiyama, S. Honda, H. Takada
  • Organizer: In Proc. of International Symposium on Electronic Design, Test and Applications (DELTA)
  • Place of Presentation: Ho Chi Minh, Vietnam
  • Year and Date: 2010-01-13
• [Presentation] Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis (2010)
  • Author(s): Toshinobu Matsuba
  • Organizer: 5th IEEE International Symposium on Electronic Design, Test & Applications
  • Place of Presentation: Ho Chi Minh, Vietnam
  • Year and Date: 2010-01-13
• [Presentation] 高位合成システムCCAPのAMPマルチコアシステム設計のための拡張 (2009)
  • Author(s): 石守祥之, 石浦菜岐佐, 冨山宏之, 神原弘之
  • Organizer: 情報処理学会SLDM/電子情報通信学会VLD/CPSY/RECONF研究会
  • Place of Presentation: 横浜
  • Year and Date: 2009-01-29
• [Presentation] The CHStone Benchmark Suite for Practical C-based High-Level Synthesis (2009)
  • Author(s): Y. Hara, H. Tomiyama, S. Honda, H. Takada
  • Organizer: ECSI and USB Workshop on High Level Synthesis: Next Step to Efficient ESL Design in conjunction with Asia and South Pacific Design Automation Conference (ASP-DAC) and ElectronicDesign and Solution Fiair (EDSFair)
  • Place of Presentation: Yokohama, Japan
  • Year and Date: 2009-01-22
• [Presentation] The CHStone Benchmark Suite for Practical C-based High-Level Synthesis (2009)
  • Author(s): Yuko Hara
  • Organizer: ECSI and USB Workshop on High-Level Synthesis : Next Step to Efficient ESL Design
  • Place of Presentation: Yokohama, Japan
  • Year and Date: 2009-01-22
• [Presentation] Behavioral Partitioning with Exploiting Function-Level Parallelism (2008)
  • Author(s): Y. Hara, H. Tomiyama, S. Honda, H. Takada, K. Ishii
  • Organizer: InProc. of International SoC Design Conference (ISOCC)
  • Place of Presentation: Busan, Korea
  • Year and Date: 2008-11-24
• [Presentation] Behavioral Partitioning with Exploiting Function-Level Parallelism (2008)
  • Author(s): Yuko Hara
  • Organizer: International SoC Design Conference
  • Place of Presentation: Busan, Korea
  • Year and Date: 2008-11-24
• [Presentation] 動作合成の動向～基礎研究から実用へ～ (2008)
  • Author(s): 冨山宏之
  • Organizer: 電子情報通信学会基礎・境界ソサイエティ大会
  • Place of Presentation: チュートリアル, 川崎
  • Year and Date: 2008-09-18
• [Presentation] 動作合成の動向〜基礎研究から実用へ〜 (2008)
  • Author(s): 冨山宏之
  • Organizer: 電子情報通信学会基礎・境界ソサイエティ大会
  • Place of Presentation: 川崎
  • Year and Date: 2008-09-18
• [Presentation] ハードウェア動作記述のSSA変換によるクロック周波数の向上 (2008)
  • Author(s): 松葉俊信, 冨山宏之, 本田晋也, 高田広章
  • Organizer: DAシンポジウム2008論文集
  • Place of Presentation: 浜松
  • Year and Date: 2008-08-26
• [Presentation] ハードウェア動作記述のSSA変換によるクロック周波数の向上 (2008)
  • Author(s): 松葉俊信
  • Organizer: DAシンポジウム
  • Place of Presentation: 浜松
  • Year and Date: 2008-08-26
• [Presentation] The CHStone Benchmark Suite for Practical C-based High-Level Synthesis (2008)
  • Author(s): Y. Hara, H. Tomiyama, S. Honda, H. Takada
  • Organizer: Poster presentation at ECSI Workshop on High-Level Synthesis: Back to the Future in conjunction with Design Automation Conference (DAC)
  • Place of Presentation: Anaheim, CA, USA
  • Year and Date: 2008-06-08
• [Presentation] The CHStone Benchmark Suite for Practical C-based High-Level Synthesis (2008)
  • Author(s): Yuko Hara
  • Organizer: ECSI Workshop on High-Level Synthesis : Back to the Future
  • Place of Presentation: Anaheim, CA, USA
  • Year and Date: 2008-06-08
• [Presentation] CHStone: A Benchmark Program Suite for Practical C-Based High-Level Synthesis (2008)
  • Author(s): Y. Hara, H. Tomiyama, S. Honda, H. Takada, K. Ishii
  • Organizer: In Proc. of International Symposium on Circuits and Systems (ISCAS)
  • Place of Presentation: Seattle, WA, USA
  • Year and Date: 2008-05-19
• [Presentation] CHStone : A Benchmark Program. Suite for Practical C-Based High-Level Synthesis (2008)
  • Author(s): Yuko Hara
  • Organizer: International Symposium on Circuits and Systems
  • Place of Presentation: Seattle, WA, USA
  • Year and Date: 2008-05-19
• [Presentation] Partitioning Behavioral Descriptions Exploiting Function-Level Parallelism (2008)
  • Author(s): Y. Hara, H. Tomiyama, S. Honda, H. Takada, K. Ishii
  • Organizer: 組込技術とネットワークに関するワークショップ(ETNET)
  • Place of Presentation: 屋久島
  • Year and Date: 2008-03-27
• [Presentation] Partitioning Behavioral Descriptions Exploiting Function-level Parallelism (2008)
  • Author(s): Yuko Hara
  • Organizer: 組込技術とネットワークに関するワークショップ
  • Place of Presentation: 屋久島
  • Year and Date: 2008-03-27
• [Presentation] Hardware/Software Covalidation with FPGA and RTOS Model (2007)
  • Author(s): S. Shibata, S. Honda, Y. Hara, H. Tomiyama, H. Takada
  • Organizer: InProc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI)
  • Place of Presentation: Sapporo, Japan
  • Year and Date: 2007-10-16
• [Presentation] Calling Software Functions from Hardware Functions in High-Level Synthesizer CCAP (2007)
  • Author(s): M. Nishimura, N. Ishiura, Y. Ishimori, H. Kanbara, H. Tomiyama
  • Organizer: In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI)
  • Place of Presentation: Sapporo, Japan
  • Year and Date: 2007-10-16
• [Presentation] Calling Software Functions from Hardware Functions in High-Level Synthesizer CCAP (2007)
  • Author(s): Masanari Nishimura
  • Organizer: 14th Workshop on Synthesis And System Integration of Mixed Information technologies
  • Place of Presentation: 札幌
  • Year and Date: 2007-10-16
• [Presentation] Hardware/Software Covalidation with FPGA and RTOS Model (2007)
  • Author(s): Seiya Shibata
  • Organizer: 14th Workshop on Synthesis And System Integration of Mixed Information technologies
  • Place of Presentation: 札幌
  • Year and Date: 2007-10-16
• [Presentation] Speed Improvement of AES Encryption using Hardware Acclererators Synthesized by C Compatible Architecture Prototyper (CCAP) (2007)
  • Author(s): H. Kanbara, T. Nakatani, N. Umehara, N. Ishiura, H. Tomiyama
  • Organizer: In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI)
  • Place of Presentation: Sapporo, Japan
  • Year and Date: 2007-10-15
• [Presentation] Speed Improvement of AES Encryption using Hardware Acclererators Synthesized by C Compatible Architecture Prototyper (CCAP) (2007)
  • Author(s): Hiroyuki Kanbara
  • Organizer: 14th Workshop on Synthesis And System Integration of Mixed Information technologies
  • Place of Presentation: 札幌
  • Year and Date: 2007-10-15
• [Presentation] CHStone:Cベース高位合成のためのベンチマークスイート (2007)
  • Author(s): 原祐子, 冨山宏之, 本田晋也, 高田広章, 石井克哉
  • Organizer: DAシンポジウム2007論文集
  • Place of Presentation: 浜松
  • Year and Date: 2007-08-30
• [Presentation] CHStone:Cベース高位合成のためのベンチマークスイート (2007)
  • Author(s): 原 祐子
  • Organizer: DAシンポジウム
  • Place of Presentation: 浜松
  • Year and Date: 2007-08-30
• [Remarks]
  • URL: http://hiroyuki.tomiyama-lab.org/publications
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  • URL: http://kenpro.mynu.jp:8001/Profiles/0026/0002632/profile.html
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  • URL: http://sites.google.com/site/hiroyukitomiyama/publications