Development of very low-power dynamically reconfigurable microprocessors with nonvolatile memories
| Project/Area Number |
19760229
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
YAMAMOTO Shuu'ichirou Tokyo Institute of Technology, 大学院・総合理工学研究科, 助教 (50313375)
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| Project Period (FY) |
2007 – 2009
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| Project Status |
Completed (Fiscal Year 2009)
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| Budget Amount *help |
¥3,780,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥480,000)
Fiscal Year 2009: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2008: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2007: ¥1,700,000 (Direct Cost: ¥1,700,000)
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| Keywords | マイクロプロセッサ / 動的再構成論理回路 / 不揮発性メモリ / 電源遮断 / 低消費電力 |
|---|
| Research Abstract |
In order to develop microprocessors with very low-power consumption and high performance, novel nonvolatile memory circuits have been proposed, designed and analyzed. Evaluation of the circuits was done by a circuit simulator. Dynamically reconfigurable microprocessors that can execute information processing with very high speed using limited circuit layout area were designed. Utilization method of the nonvolatile memory circuits in the dynamically reconfigurable microprocessors was proposed. Consequently, basis of developing very low-power dynamically reconfigurable microprocessors with nonvolatile memories have been established.
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Report
(4 results)
Research Products
(38 results)
