Scalable Silicon Quantum Dots with Stacked Layered Structures for 3D Integration

• Project/Area Number: 19H00754
• Research Category: Grant-in-Aid for Scientific Research (A)
• Allocation Type: Single-year Grants
• Section: 一般
• Review Section: Medium-sized Section 21:Electrical and electronic engineering and related fields
• Research Institution: The University of Tokyo
• Principal Investigator: Hiramoto Toshiro 東京大学, 生産技術研究所, 教授 (20192718)
• Project Period (FY): 2019-04-01 – 2023-03-31
• Project Status: Completed (Fiscal Year 2023)
• Budget Amount: ¥45,110,000 (Direct Cost: ¥34,700,000、Indirect Cost: ¥10,410,000); Fiscal Year 2022: ¥10,270,000 (Direct Cost: ¥7,900,000、Indirect Cost: ¥2,370,000); Fiscal Year 2021: ¥10,270,000 (Direct Cost: ¥7,900,000、Indirect Cost: ¥2,370,000); Fiscal Year 2020: ¥11,570,000 (Direct Cost: ¥8,900,000、Indirect Cost: ¥2,670,000); Fiscal Year 2019: ¥13,000,000 (Direct Cost: ¥10,000,000、Indirect Cost: ¥3,000,000)
• Keywords: シリコン量子ビット / 量子コンピュータ / シリコン量子ドット / 大規模集積回路 / 単電子トランジスタ / シリコンナノワイヤトランジスタ / 三次元集積化

Outline of Research at the Start

本研究では，シリコン量子ビットのスケーラブルな三次元集積化を目指して，積層構造の集積量子ビットを提案する．量子計算では論理値を増やし量子誤り訂正等を行うため，量子ビット数を増やすことが必須であるが，従来研究は複数量子ビットを一次元配列したものが多く，スケーラビリティに限界があった．本研究では，三次元にスケーラブルに拡張可能な構造として，Si/SiGe積層膜プロセスを利用して縦に量子ビットを積む積層量子ビットを提案する．

Outline of Final Research Achievements

This study aims at the demonstration of the idea of scalable silicon quantum bits with stacked layers for 3D integration. Combining stacked silicon channel formation process by Si/SiGe epitaxial layers and nanofabirication process by electron beam lithography, the eight-dot structure with four quantum dots in the upper layers and four quantum dots in the lower layers were successfully formed. The fabricated devices were measured at low temperature and the adjacent single electron transistors showed the capacitance coupling effects, suggesting that the proposed stacked structure will be suitable for the 3D integration.

Academic Significance and Societal Importance of the Research Achievements

実用的な量子コンピュータではエラー訂正等のため極めて多数の量子ビットが必要となり，量子ビットの集積化は今後の大きな課題であった．本研究は，大多数の量子ビット集積化のために量子ビットと3次元集積化に道筋をつけたものであり，学術的意義および社会的意義は大きい．

Research Products

• [Journal Article] Subthreshold Swing in Silicon Gate-All-Around Nanowire and Fully Depleted SOI MOSFETs at Cryogenic Temperature (2021)
  • Author(s): Sekiguchi Shohei、Ahn Min-Ju、Mizutani Tomoko、Saraya Takuya、Kobayashi Masaharu、Hiramoto Toshiro
  • Journal Title: IEEE Journal of the Electron Devices Society Volume: 9 Pages: 1151-1154
  • DOI: 10.1109/jeds.2021.3108854
  • Peer Reviewed / Open Access
• [Presentation] 高集積 3 次元積層シリコン量子ビットにおける量子ドットの個別制御 (2024)
  • Author(s): 二木大輝
  • Organizer: 第71回応用物理学会春季学術講演会
• [Presentation] Individual Control of Characteristics of Vertically Stacked Silicon Quantum Dots (2023)
  • Author(s): Junoh Kim
  • Organizer: Silicon Electronics Workshop (SNW)
  • Int'l Joint Research
• [Presentation] 3D architecture for high-density silicon qubits by vertically stacked layers and common electrodes (2023)
  • Author(s): Daiki Futagi
  • Organizer: Silicon Quantum Electronics Workshop (SiQEW)
  • Int'l Joint Research
• [Presentation] 三次元積層型シリコン量子ドットの特性の個別制御 (2023)
  • Author(s): 金 駿午
  • Organizer: 第84回応用物理学会秋季学術講演会
• [Presentation] シリコンダブル量子ドットの作製と低温特性評価 (2023)
  • Author(s): 金 駿午
  • Organizer: 第70回応用物理学会春季学術講演会
• [Presentation] Subthreshold Swing in Silicon Gate-All-Around Nanowire MOSFET at Cryogenic Temperature (2021)
  • Author(s): Shohei Sekiguchi
  • Organizer: Electron Devices Technology and Manufacturing Conference (EDTM)
  • Int'l Joint Research
• [Presentation] シリコンGAAナノワイヤMOSFETの低温サブスレッショルド特性 (2021)
  • Author(s): 関口翔平
  • Organizer: 第68回応用物理学会春季学術講演会