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Study on tunnel field effect transistors for ultra-low power analog devices

Research Project

Project/Area Number 19K21084
Project/Area Number (Other) 18H05913 (2018)
Research Category

Grant-in-Aid for Research Activity Start-up

Allocation TypeMulti-year Fund (2019)
Single-year Grants (2018)
Review Section 0302:Electrical and electronic engineering and related fields
Research InstitutionTokyo Institute of Technology (2019)
National Institute of Information and Communications Technology

Principal Investigator

GOTOW TAKAHIRO  東京工業大学, 工学院, 助教 (70827914)

Project Period (FY) 2018-08-24 – 2020-03-31
Project Status Completed (Fiscal Year 2019)
Budget Amount *help
¥2,990,000 (Direct Cost: ¥2,300,000、Indirect Cost: ¥690,000)
Fiscal Year 2019: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2018: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
KeywordsTFET / MOS界面準位 / GaAsSb / InGaAs
Outline of Research at the Start

従来型MOSFETと比較して理論的に極低電圧動作が期待できるトンネルトランジスタはロジックLSI応用のみならず、アナログデバイスとしても期待されている。トンネルトランジスタの構成材料としてはGaAsSb/InGaAsヘテロ構造が有望である。本研究では、GaAsSb/InGaAs TFETの試作と2次元TCADシステムを用いた理論計算を組み合わせることで、トンネルトランジスタの将来の通信デバイス適用のための基礎検討を行う。

Outline of Final Research Achievements

Tunnel field-effect transistors (TFETs) have been widely studied as promising candidates for steep slope devices. Among them, the Type-II heterojunction TFET that uses GaAsSb as the source and InGaAs as the channel is the most promising from a material standpoint. In addition, from the viewpoint of the device structure, it is essential to adopt a nanosheet channel structure that enables lateral miniaturization of the source/channel junction. We fabricated a nanosheet channel InGaAs MOSFET and evaluated the mobility of InGaAs channel. These technologies accelerate the study of the nanosheet channel TFETs.

Academic Significance and Societal Importance of the Research Achievements

本研究のトランジスタはアナログ・ロジック回路の最も重要な構成要素の1つであり、極低消費電力化と高速化を両立させようという取り組みである。また、今回の横型デバイスはこれまでのSiプラットフォームへの適用も可能であり汎用性が高い。製品応用を視野に入れると低消費電力素子が必要な分野は多く存在する。センサネットワークや発電可能な集積回路など、章補電力を極限的に下げることへの要請は数多く存在する。そのため、トンネルFETの実用化により、これまでの半導体集積回路技術では実現出来なかった新たな応用分野が広がっていくと考えられる。

Report

(2 results)
  • 2019 Final Research Report ( PDF )
  • 2018 Annual Research Report
  • Research Products

    (6 results)

All 2019 2018

All Journal Article (2 results) (of which Peer Reviewed: 1 results) Presentation (4 results) (of which Int'l Joint Research: 3 results)

  • [Journal Article] Drive current enhancement of Si MOSFETs by using anti-ferroelectric gate insulators2019

    • Author(s)
      Yamaguchi Masashi、Gotow Takahiro、Takenaka Mitsuru、Takagi Shinichi
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 58 Issue: SB Pages: SBBA15-SBBA15

    • DOI

      10.7567/1347-4065/ab073b

    • Related Report
      2018 Annual Research Report
    • Peer Reviewed
  • [Journal Article] 材料エンジニアリングによるトンネル電界効果トランジスタの高性能化2019

    • Author(s)
      (2)高木信一, 加藤公彦, 安大煥, 後藤高寛, 松村亮, 高口遼太郎, 竹中充
    • Journal Title

      電子情報通信学会論文誌 C

      Volume: Vol. J102-C, NO.3 Pages: 61-69

    • Related Report
      2018 Annual Research Report
  • [Presentation] InP基板上引張歪GaAsSbとInGaAsの膜厚増加による結晶性劣化の比較2019

    • Author(s)
      満原学, 星拓也, 杉山弘樹, 後藤高寛, 竹中充, 高木信一
    • Organizer
      第66回応用物理学会春季学術講演会
    • Related Report
      2018 Annual Research Report
  • [Presentation] Improvement of ION and S.S. values of p-GaAs0.51Sb0.49/In0.53Ga0.47As hetero-junction vertical TFETs by using abrupt source impurity profile2018

    • Author(s)
      T. Gotow, M. Mitsuharu, T. Hoshi, H. Sugiyama, M. Takenaka, S. Takagi
    • Organizer
      International Conference on Solid State Devices and Materials (SSDM)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Performance enhancement of Si MOSFETs using anti-ferroelectric thin films as gate insulators2018

    • Author(s)
      M. Yamaguchi, T. Gotow, M. Takenaka, S. Takagi
    • Organizer
      International Conference on Solid State Devices and Materials (SSDM)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] MOS Device Technology using Alternative Channel Materials for Low Power Logic LSI2018

    • Author(s)
      (5)S. Takagi, K. Kato, W.-K. Kim, K. Jo, R. Matsumura, R. Takaguchi, D.-H. Ahn, T. Gotow, M. Takenaka
    • Organizer
      48th European Solid-State Device Research Conference (ESSDERC)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research

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Published: 2018-08-27   Modified: 2024-03-26  

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