Architecture Design Method for Multi-processor SoC
| Project/Area Number |
20300017
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Osaka University |
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Principal Investigator |
IMAI Masaharu 大阪大学, 大学院・情報科学研究科, 教授 (50126926)
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| Co-Investigator(Kenkyū-buntansha) |
TAKEUCHI Yoshinori 大阪大学, 大学院・情報科学研究科, 准教授 (70242245)
SAKANUSHI Keishi 大阪大学, 大学院・情報科学研究科, 助教 (00346173)
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| Project Period (FY) |
2008 – 2011
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| Project Status |
Completed (Fiscal Year 2011)
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| Budget Amount *help |
¥19,110,000 (Direct Cost: ¥14,700,000、Indirect Cost: ¥4,410,000)
Fiscal Year 2011: ¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2010: ¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2009: ¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2008: ¥5,590,000 (Direct Cost: ¥4,300,000、Indirect Cost: ¥1,290,000)
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| Keywords | VLSI設計技術 / MPSoC / マルチコア / マルチプロセッサ / IPベース設計 / DVFS / MPSoC (マルチプロセッサSoC) / MPSoC(マルチプロセッサSoC) / マルチコアSoC / 設計最適化 |
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| Research Abstract |
This research proposed a new exploration method for Multi-Processor SoC architecture and task assignment optimization method, and implemented these methods as prototype design tools. Experimental results show that the proposed method can find solutions that are same quality as the optimal solutions in short time
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Report
(6 results)
Research Products
(21 results)
