Basic Studies on Testability and Security for Network-on-Chip

• Project/Area Number: 20300018
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Nara Institute of Science and Technology
• Principal Investigator: FUJIWARA Hideo Nara Institute of Science and Technology, 情報科学研究科, 教授 (70029346)
• Co-Investigator(Kenkyū-buntansha): INOUE Michiko 奈良先端科学技術大学院大学, 情報科学研究科, 准教授 (30273840) ; OHTAKE Satoshi 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (20314528) ; YONEDA Tomokazu 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (20359871)
• Project Period (FY): 2008 – 2010
• Project Status: Completed (Fiscal Year 2010)
• Budget Amount: ¥13,390,000 (Direct Cost: ¥10,300,000、Indirect Cost: ¥3,090,000); Fiscal Year 2010: ¥2,990,000 (Direct Cost: ¥2,300,000、Indirect Cost: ¥690,000); Fiscal Year 2009: ¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000); Fiscal Year 2008: ¥6,110,000 (Direct Cost: ¥4,700,000、Indirect Cost: ¥1,410,000)
• Keywords: VLSI設計技術 / VLSIのテスト / ネットワークオンチップ / テスト容易性 / 安全性(セキュリティ) / スキャン設計 / システムオンチップ / ディペンダブルコンピューティング / 高信頼性ネットワーク / 設計自動化

Research Abstract

(1) We proposed a design-for-test method for functional RTL circuits (called F-Scan) and showed the effectiveness by using benchmarks. (2) We proposed an ATPG and DFT method for asynchronous circuits used in Network-on-Chip. (3) We introduced a new concept of shift-register equivalence and proposed a secure scan method that satisfies both testability and security and clarified the security level analytically.

Research Products

• [Journal Article] F-Scan : A DFT Method for Functional Scan at RTL (2011)
  • Author(s): Marie Engelene Jimenez Obien, Satoshi Ohtake, Hideo Fujiwara
  • Journal Title: IEICE Trans. on Inf. and Syst. Vol.E94-D, No.1 Pages: 104-113
  • NAID: 10027989592
  • Peer Reviewed
• [Journal Article] F-Scan : A DFT Method for Functional Scan at RTL (2011)
  • Author(s): Marie Engelene Jimenez Obien
  • Journal Title: IEICE Trans.on Inf.and Syst. Volume: E94-D Pages: 104-113
  • Peer Reviewed
• [Journal Article] An Approach for Verification Assertions Reuse in RTL Test Pattern Generation (2010)
  • Author(s): Maksim Jenihhin, Jaan Raik, Raimund Ubar, Taavi Viilukas, Hideo Fujiwara
  • Journal Title: Journal of Shanghai Normal University Vol.39, No.5 Pages: 441-447
  • Peer Reviewed
• [Journal Article] セキュアスキャン設計のためのシフトレジスタ等価回路の列挙と合成 (2010)
  • Author(s): 藤原克哉、藤原秀雄、オビエン・マリー・エンジェリン, 玉本英夫
  • Journal Title: 電子情報通信学会和文論文誌D-I Vol.J93-D, No.11 Pages: 2426-2436
  • NAID: 110007880365
  • Peer Reviewed
• [Journal Article] A New Class of Easily Testable Assignment Decision Diagram (2010)
  • Author(s): Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'ameri, Hideo Fujiwara
  • Journal Title: Malayaisan Journal Computer Science Vol.23, No.1 Pages: 1-17
  • Peer Reviewed
• [Journal Article] A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification (2010)
  • Author(s): Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
  • Journal Title: IEICE Trans. on Information and Systems Vol.E93-D, No.7 Pages: 1857-1865
  • NAID: 10027363954
  • Peer Reviewed
• [Journal Article] Design and Optimization of Transparency-Based TAM for SoC Test (2010)
  • Author(s): Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
  • Journal Title: IEICE Trans. on Inf. and Syst. Vol.E93-D, No.6 Pages: 1549-1559
  • NAID: 10027987897
  • Peer Reviewed
• [Journal Article] RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences (2010)
  • Author(s): Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara
  • Journal Title: Journal of Electronic Testing : Theory and Applications Volume 26, Issue 2 Pages: 151-164
  • Peer Reviewed
• [Journal Article] A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint (2010)
  • Author(s): Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol.E93-D, No.1 Pages: 24-32
  • NAID: 10026812987
  • Peer Reviewed
• [Journal Article] RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences (2010)
  • Author(s): Hongxia Fang
  • Journal Title: Journal of Electronic Testing : Theory and Applications Volume: 26 Pages: 151-164
  • Peer Reviewed
• [Journal Article] Design and Optimization of Transparency-Based TAM for SoC Test (2010)
  • Author(s): Tomokazu Yoneda
  • Journal Title: IEICE Trans.on Inf.and Syst. Volume: E93-D Pages: 1549-1559
  • NAID: 10027987897
  • Peer Reviewed
• [Journal Article] A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification (2010)
  • Author(s): Hiroshi Iwata
  • Journal Title: IEICE Trans.on Inf.and Syst. Volume: E93-D Pages: 1857-1865
  • Peer Reviewed
• [Journal Article] セキュアスキャン設計のためのシフトレジスタ等価回路の列挙と合成 (2010)
  • Author(s): 藤原克哉
  • Journal Title: 電子情報通信学会和文論文誌D-I Volume: J93-D Pages: 2426-2436
  • NAID: 110007880365
  • Peer Reviewed
• [Journal Article] 部分スルー可検査性に基づく順序回路のテスト生成法 (2009)
  • Author(s): 岡伸也, Chia Yee Ooi, 市原英行, 井上智生, 藤原秀雄
  • Journal Title: 電子情報通信学会和文論文誌D-I Vol.J92-D, No.12 Pages: 2207-2216
  • NAID: 110007482414
  • Peer Reviewed
• [Journal Article] 部分スルー可検査性に基づく順序回路のテスト生成法 (2009)
  • Author(s): 岡伸也
  • Journal Title: 電子情報通信学会和文論文誌D-I J92-D Pages: 2207-2216
  • Peer Reviewed
• [Journal Article] A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint (2009)
  • Author(s): Ryoichi Inoue
  • Journal Title: IEICE Transactions on Information and Systems E93-D Pages: 24-32
  • Peer Reviewed
• [Journal Article] Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips (2008)
  • Author(s): Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.10 Pages: 2440-2448
  • NAID: 10026805953
  • Peer Reviewed
• [Journal Article] A Non-Scan Design-for-Testability for Register-Transfer Level Circuits to Guarantee Linear-Depth Time Expansion Models (2008)
  • Author(s): Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi
  • Journal Title: IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems Vol.27, No.9 Pages: 1535-1544
  • Peer Reviewed
• [Journal Article] NoC-compatible Wrapper Design and Optimization Under Channel Bandwidth and Test Time Constraints (2008)
  • Author(s): Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.7 Pages: 2008-2017
  • NAID: 10026805045
  • Peer Reviewed
• [Journal Article] On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time (2008)
  • Author(s): Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.7 Pages: 1999-2007
  • NAID: 10026805015
  • Peer Reviewed
• [Journal Article] On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time (2008)
  • Author(s): Fawnizu Azmadi Hussin
  • Journal Title: IEICE Trans, on Informat ion & Sys terns E91-D Pages: 1999-2007
  • Peer Reviewed
• [Journal Article] NoC-compatible Wrapper Design and Optimization Under Channel Bandwidth and Test Time Constraints (2008)
  • Author(s): Fawnizu Azmadi Hussin
  • Journal Title: IEICE Trans. on Inforiat ion & Systems E91-D Pages: 2008-2017
  • Peer Reviewed
• [Journal Article] A Non-Scan Design-for-Testability for Register-Transfer Level Circuits to Guarantee Linear-Depth Time Expansion Models (2008)
  • Author(s): Hideo Fuj iwara
  • Journal Title: IEEE Trans, on Compu ter-Aided Des ignof Integrated Circuits and Sys terns 27 Pages: 1535-1544
  • Peer Reviewed
• [Journal Article] Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips (2008)
  • Author(s): Thomas Edison Yu
  • Journal Title: IEICE Trans, on Information &Systems E91-D Pages: 2440-2448
  • Peer Reviewed
• [Presentation] Secure Scan Design Using Shift Register Equivalents against Differential Behavior Attack (2011)
  • Author(s): Hideo Fujiwara
  • Organizer: 16th Asia and South Pacific Design Automation Conference
  • Place of Presentation: 横浜
  • Year and Date: 2011-01-28
• [Presentation] Secure Scan Design Using Shift Register Equivalents against Differential Behavior Attack (2011)
  • Author(s): Hideo Fujiwara, Katsuya Fujiwara, Hideo Tamamoto
  • Organizer: 16th Asia and South Pacific Design Automation Conference
• [Presentation] RedSOCs-3D : Thermal-safe Test Scheduling for 3D-Stacked SoC (2010)
  • Author(s): Fawnizu Azmadi Hussin
  • Organizer: 2010 Asia Pacific Conference on Circuits and Systems
  • Place of Presentation: クアラルンプール、マレーシア
  • Year and Date: 2010-12-10
• [Presentation] SREEP-2 : SR-Equivalent Generator for Secure and Testable Scan Design (2010)
  • Author(s): Katsuya Fujiwara
  • Organizer: 11th IEEE workshop on RTL and High Level Testing
  • Place of Presentation: 上海、中国
  • Year and Date: 2010-12-06
• [Presentation] Functional Fault Model for Micro Operation Faults of High Correlation with Stuck-At Faults (2010)
  • Author(s): Chia Yee Ooi
  • Organizer: 11th IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: 上海、中国
  • Year and Date: 2010-12-06
• [Presentation] An Approach for Verification Assertions Reuse in RTL Test Pattern Generation (2010)
  • Author(s): Maksim Jenihhin
  • Organizer: 11th IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: 上海、中国
  • Year and Date: 2010-12-06
• [Presentation] Bipartite Full Scan Design : A DFT Method for Asynchronous Circuits (2010)
  • Author(s): Hiroshi Iwata
  • Organizer: IEEE the 19th Asian Test Symposium
  • Place of Presentation: 上海、中国
  • Year and Date: 2010-12-02
• [Presentation] Seed Ordering and Selection for High Quality Delay Test (2010)
  • Author(s): Tomokazu Yoneda
  • Organizer: IEEE the 19th Asian Test Symposium
  • Place of Presentation: 上海、中国
  • Year and Date: 2010-12-02
• [Presentation] Capture in Turn Scan for Reduction of Test Date Volume, Test Application Time and Test Power (2010)
  • Author(s): Zhiqiang You
  • Organizer: IEEE the 19th Asian Test Symposium
  • Place of Presentation: 上海、中国
  • Year and Date: 2010-12-02
• [Presentation] Constrained ATPG for Functional RTL Circuits Using F-Scan (2010)
  • Author(s): Marie Engelene J.Obien
  • Organizer: 2010 IEEE International Test Conference
  • Place of Presentation: Austin, USA
  • Year and Date: 2010-11-04
• [Presentation] RT-Level Design-for-Testability and Expansion of Functional Test Sequences for Enhanced Defect Coverage (2010)
  • Author(s): Alodeep Sanyal
  • Organizer: 2010 IEEE International Test Conference
  • Place of Presentation: Austin, USA
  • Year and Date: 2010-11-04
• [Presentation] Delay Fault ATPG for F-Scannable RTL Circuits (2010)
  • Author(s): Marie Engelene Jimenez Obien
  • Organizer: IEEE Int.Symp.on Communications and Information Technologies
  • Place of Presentation: 東京
  • Year and Date: 2010-10-28
• [Presentation] Aging Test Strategy and Adaptive Test Scheduling for SoC Failure Prediction (2010)
  • Author(s): Hyunbean Yi
  • Organizer: IEEE International On-Line Testing Symposium
  • Place of Presentation: Corfu Island, Greece
  • Year and Date: 2010-07-06
• [Presentation] Scan Cells Reordering to Minimize Peak Power during Test Cycle : A Graph Theoretic Approach (2010)
  • Author(s): Jaynarayan Tudu
  • Organizer: 2010 IEEE European Test Symposium
  • Place of Presentation: Prague, Czech Republic
  • Year and Date: 2010-05-25
• [Presentation] Test Pattern Selection to Optimize Delay Test Quality with a Limited Size of Test Set (2010)
  • Author(s): Michiko Inoue
  • Organizer: 2010 IEEE European Test Symposium
  • Place of Presentation: Prague, Czech Republic
  • Year and Date: 2010-05-25
• [Presentation] Thermal-Uniformity-Aware X-Filling to Reduce Temperature-Induced Delay Variation for Accurate At-Speed Testing (2010)
  • Author(s): Tomokazu Yoneda
  • Organizer: 28th IEEE VLSI Test Symposium
  • Place of Presentation: Santa Cruz, USA
  • Year and Date: 2010-04-19
• [Presentation] SREEP : Shift Register Equivalents Enumeration and Synthesis Program for Secure Scan Design (2010)
  • Author(s): Katsuya Fujiwara
  • Organizer: 13th IEEE International Symposium on Design and Diagnosis of Electronic Circuits and Systems
  • Place of Presentation: Vienna, Austria
  • Year and Date: 2010-04-15
• [Presentation] A Synthesis Method to Propagate False Path Information from RTL to Gate Level (2010)
  • Author(s): Satoshi Ohtake
  • Organizer: 13th IEEE International Symposium on Design and Diagnosis of Electronic Circuits and Systems
  • Place of Presentation: Vienna, Austria
  • Year and Date: 2010-04-15
• [Presentation] Secure and Testable Scan Design Using Extended de Bruijn Graphs (2010)
  • Author(s): Hideo Fujiwara
  • Organizer: 15th Asia and South Pacific Design Automation Conference
  • Place of Presentation: Taipei, Taiwan
  • Year and Date: 2010-01-19
• [Presentation] Enhancing False Path Identification from RTL for Reducing Design and Test Futileness (2010)
  • Author(s): Hiroshi Iwata
  • Organizer: The 5th IEEE International Symposium on Electronic Design, Test & Applications
  • Place of Presentation: Ho Chi Minh City, Vietnam
  • Year and Date: 2010-01-14
• [Presentation] On Minimization of Test Application Time for RAS (2010)
  • Author(s): Raghavendra Adiga
  • Organizer: 23rd Internaional Conference on VLSI Design
  • Place of Presentation: Bangalore, India
  • Year and Date: 2010-01-05
• [Presentation] RedSOCs-3D : Thermal-safe Test Scheduling for 3D-Stacked SoC (2010)
  • Author(s): Fawnizu Azmadi Hussin, Thomas Edison Chua Yu, Tomokazu Yoneda, Hideo Fujiwara
  • Organizer: 2010 Asia Pacific Conference on Circuits and Systems
• [Presentation] An Approach for Verification Assertions Reuse in RTL Test Pattern Generation (2010)
  • Author(s): Maksim Jenihhin, Jaan Raik, Hideo Fujiwara, Raimund Ubar, Taavi Viilukas
  • Organizer: 11th IEEE Workshop on RTL and High Level Testing
• [Presentation] Functional Fault Model for Micro Operation Faults of High Correlation with Stuck-At Faults (2010)
  • Author(s): Chia Yee Ooi, Hideo Fujiwara
  • Organizer: 11th IEEE Workshop on RTL and High Level Testing
• [Presentation] SREEP-2 : SR-Equivalent Generator for Secure and Testable Scan Design (2010)
  • Author(s): Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto
  • Organizer: 11th IEEE Workshop on RTL and High Level Testing
• [Presentation] Capture in Turn Scan for Reduction of Test Date Volume, Test Application Time and Test Power (2010)
  • Author(s): Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara
  • Organizer: Proc. of IEEE the 19th Asian Test Symposium
• [Presentation] Seed Ordering and Selection for High Quality Delay Test (2010)
  • Author(s): Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara
  • Organizer: Proc. of IEEE the 19th Asian Test Symposium
• [Presentation] Bipartite Full Scan Design : A DFT Method for Asynchronous Circuits (2010)
  • Author(s): Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
  • Organizer: Proc. of IEEE the 19th Asian Test Symposium
• [Presentation] RT-Level Design-for-Testability and Expansion of Functional Test Sequences for Enhanced Defect Coverage (2010)
  • Author(s): Alodeep Sanyal, Krishnendu Chakrabarty, Mahmt Yilmaz, Hideo Fujiwara
  • Organizer: 2010 IEEE International Test Conference
• [Presentation] Constrained ATPG for Functional RTL Circuits Using F-Scan (2010)
  • Author(s): Marie Engelene J.Obien, Satoshi Ohtake, Hideo Fujiwara
  • Organizer: 2010 IEEE International Test Conference
• [Presentation] Delay Fault ATPG for F-Scannable RTL Circuits (2010)
  • Author(s): Marie Engelene Jimenez Obien, Satoshi Ohtake, Hideo Fujiwara
  • Organizer: IEEE Int.Symp. on Communications and Information Technologies
• [Presentation] Aging Test Strategy and Adaptive Test Scheduling for SoC Failure Prediction (2010)
  • Author(s): Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
  • Organizer: IEEE International On-Line Testing Symposium
• [Presentation] Graph Theoretical Approach for Scan Cell Reordering to Minimize Peak Shift Power (2010)
  • Author(s): Jaynarayan Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
  • Organizer: ACM Great Lake Symposium on VLSI
• [Presentation] Test Pattern Selection to Optimize Delay Test Quality with a Limited Size of Test Set (2010)
  • Author(s): Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara
  • Organizer: 2010 IEEE European Test Symposium
• [Presentation] Scan Cells Reordering to Minimize Peak Power during Test Cycle : A Graph Theoretic Approach (2010)
  • Author(s): Jaynarayan Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
  • Organizer: 2010 IEEE European Test Symposium
• [Presentation] Thermal-Uniformity-Aware X-Filling to Reduce Temperature-Induced Delay Variation for Accurate At-Speed Testing (2010)
  • Author(s): Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
  • Organizer: 28th IEEE VLSI Test Symposium
• [Presentation] A Synthesis Method to Propagate False Path Information from RTL to Gate Level (2010)
  • Author(s): Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara
  • Organizer: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
• [Presentation] SREEP : Shift Register Equivalents Enumeration and Synthesis Program for Secure Scan Design (2010)
  • Author(s): Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J.Obien, Hideo Tamamoto
  • Organizer: 13th IEEE International Symposium on Design and Diagnosis of Electronic Circuits and Systems
• [Presentation] A Method of Unsensitizable Path Identification using High Level Design Information (2010)
  • Author(s): Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue, Hideo Fujiwara
  • Organizer: 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era
• [Presentation] Enhancing False Path Identification from RTL for Reducing Design and Test Futileness (2010)
  • Author(s): Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
  • Organizer: The 5th IEEE International Symposium on Electronic Design, Test & Applications
• [Presentation] Secure and Testable Scan Design Using Extended de Bruijn Graphs (2010)
  • Author(s): Hideo Fujiwara, Marie E.J.Obien
  • Organizer: 15th Asia and South Pacific Design Automation Conference
• [Presentation] On Minimization of Test Application Time for RAS (2010)
  • Author(s): Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal K.Saluja, Hideo Fujiwara, Adit D.Singh
  • Organizer: 23rd Internaional Conference on VLSI Design
• [Presentation] A DFT Method for Functional Scan at RTL (2009)
  • Author(s): Marie E.J.Obien
  • Organizer: 10th IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: Hong Kong
  • Year and Date: 2009-11-27
• [Presentation] Path-based Resource Binding to Reduce Delay Fault Test Cost (2009)
  • Author(s): Michiko Inoue
  • Organizer: 10th IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: Hong Kong
  • Year and Date: 2009-11-27
• [Presentation] Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC (2009)
  • Author(s): Jaynarayan T.Tudu
  • Organizer: 10th IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: Hong Kong
  • Year and Date: 2009-11-27
• [Presentation] Observation-Point Selection at Register-Transfer Level to Increase Defect Coverage for Functional Test Sequences (2009)
  • Author(s): Hongxia Fang
  • Organizer: 10th IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: Hong Kong
  • Year and Date: 2009-11-27
• [Presentation] RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences (2009)
  • Author(s): Hongxia Fang
  • Organizer: IEEE International High Level Design Validation and Test Workshop 2009
  • Place of Presentation: San Francisco, USA
  • Year and Date: 2009-11-05
• [Presentation] F-Scan : An Approach to Functional RTL Scan for Assignment Decision Diagrams (2009)
  • Author(s): Marie Engelene J.Obien
  • Organizer: IEEE 8th International Conference on ASIC
  • Place of Presentation: Changsha, China
  • Year and Date: 2009-10-21
• [Presentation] A Response Compactor for Extended Compatibility Scan Tree Construction (2009)
  • Author(s): Zhiqiang You
  • Organizer: IEEE 8th International Conference on ASIC
  • Place of Presentation: Changsha, China
  • Year and Date: 2009-10-21
• [Presentation] Partial Scan Approach for Secret Information Protection (2009)
  • Author(s): Michiko Inoue
  • Organizer: 2009 IEEE European Test Symposium
  • Place of Presentation: Sevilla, Spain
  • Year and Date: 2009-05-26
• [Presentation] A Synthesis Method to Alleviate Over-testing of Delay Faults Based on RTL Don't Care Path Identification (2009)
  • Author(s): Yuki Yoshikawa
  • Organizer: IEEE VTS'09 (27th VLSI Test Symposium)
  • Place of Presentation: Santa Cruz, USA
  • Year and Date: 2009-05-05
• [Presentation] Test Infrastructure Design for Core-Based System-on-Chp Under Cycle-Accurate Thermal Constraints (2009)
  • Author(s): Thomas Edison Yu
  • Organizer: 14^<th> Asian & South Pacific Design Automation Conference
  • Place of Presentation: 横浜
  • Year and Date: 2009-01-21
• [Presentation] A Response Compactor for Extended Compatibility Scan Tree Construction (2009)
  • Author(s): Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara
  • Organizer: Proc. EEE 8th International Conference on ASIC
• [Presentation] F-Scan : An Approach to Functional RTL Scan for Assignment Decision Diagrams (2009)
  • Author(s): Marie Engelene J.Obien, Hideo Fujiwara
  • Organizer: Proc.IEEE 8th International Conference on ASIC
• [Presentation] Test Generation and DFT Based on Partial Thru Testability (2009)
  • Author(s): Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
  • Organizer: 2009 IEEE European Test Symposium, poster session
• [Presentation] Partial Scan Approach for Secret Information Protection (2009)
  • Author(s): Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
  • Organizer: 2009 IEEE European Test Symposium
• [Presentation] A Synthesis Method to Alleviate Over-testing of Delay Faults Based on RTL Don't Care Path Identification (2009)
  • Author(s): Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
  • Organizer: IEEE 27th VLSI Test Symposium
• [Presentation] Test Infrastructure Design for Core-Based System-on-Chip Under Cycle-Accurate Thermal Constraints (2009)
  • Author(s): Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
  • Organizer: 14th Asia and South Pacific Design Automation Conference
• [Presentation] Fast False Path Identification Based on Functional Unsensitizability Using RTL Information (2009)
  • Author(s): Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
  • Organizer: 14th Asia and South Pacific Design Automation Conference
• [Presentation] A reconfigurable wrapper design for multi-clock domain cores (2008)
  • Author(s): Takashi Yoshida
  • Organizer: 9^<th> IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: 札幌
  • Year and Date: 2008-11-27
• [Presentation] Enhancement of test environinent generation for assignment decision diagrams (2008)
  • Author(s): Hideo Fuj iwara
  • Organizer: 9^<th> IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: 札幌
  • Year and Date: 2008-11-27
• [Presentation] A new class of easily testable assignment decision diagrams (2008)
  • Author(s): Nor 1 ina Paraman
  • Organizer: 9^<th> IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: 札幌
  • Year and Date: 2008-11-27
• [Presentation] Untes table Fault Identification in Seauential Circuits Using Model-Checking (2008)
  • Author(s): Jaan Raik
  • Organizer: 17^<th> IEEE Asian Test Symposium
  • Place of Presentation: 札幌
  • Year and Date: 2008-11-25
• [Presentation] Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-Cycle Paths (2008)
  • Author(s): Thomas Edi son Yu
  • Organizer: 17^<th> IEEE Asian Test Symposium
  • Place of Presentation: 札幌
  • Year and Date: 2008-11-25
• [Presentation] Bidirectional Delay Test of FPGA Routing Networks (2008)
  • Author(s): El ena Hammari
  • Organizer: 13th IEEE European Test Symposium
  • Place of Presentation: Lao Maggiore, イタリア
  • Year and Date: 2008-05-26
• [Presentation] Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-Cycle Paths (2008)
  • Author(s): Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
  • Organizer: Proc. of IEEE the 17th Asian Test Symposium
• [Presentation] Untestable Fault Identification in Sequential Circuits Using Model-Checking (2008)
  • Author(s): Jaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko
  • Organizer: Proc. of IEEE the 17th Asian Test Symposium
• [Remarks] ホームページ等
  • URL: http://hideo.fujiwaralab.net/
• [Remarks]
  • URL: http://hideo.fujiwaralab.net/
• [Remarks]
  • URL: http://fan.naist.jp/
• [Remarks]
  • URL: http://fan.naist.jp/