| Project/Area Number |
20500056
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Meiji University |
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Principal Investigator |
IGUCHI Yukihiro Meiji University, 理工学部, 教授 (60201307)
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| Project Period (FY) |
2008 – 2010
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| Project Status |
Completed (Fiscal Year 2010)
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| Budget Amount *help |
¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000)
Fiscal Year 2010: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2009: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2008: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Keywords | プログラマブル・ロジック・コントローラ / PLC / FPGA / 冗長剰余数系 / 基数変換 / 多値論理 / CUDA / Residue number system / reconfiurable system / 情報システム / アルゴリズム / 超高速情報処理 / 計算機システム |
|---|
| Research Abstract |
Programmable Logic Controllers (PLCs) are used for factory automation systems, amusement park rides, etc. Faster, lower-cost, and more dependable PLCs are required. The original architecture proposed by me achieved 40 times faster speed than the commercial PLC (KV-1000). I also proposed methods for the higher dependability based on residue number systems. I implemented the architecture on the consumer FPGA. I announced their development at international conferences. In February 2011, I and my student, Mr. Takahashi developed a novel architecture for PLCs. We are now developing the prototype system, and verifying the performance. Preliminary experimental results show that it will have 200 times faster one than the commercial PLCs. We are now preparing papers for international conferences held in 2012 and journals published in 2013.
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