| Project/Area Number |
20500765
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Science education
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| Research Institution | Tokyo National College of Technology |
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Principal Investigator |
KAGE Tetsuro Tokyo National College of Technology, 電子工学科, 教授 (30390420)
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| Co-Investigator(Kenkyū-buntansha) |
OHTSUKA Tomohiko 東京工業高等専門学校, 電子工学科, 教授 (80262278)
KOIKE Kiyoyuki 東京工業高等専門学校, 電子工学科, 教授 (20283038)
YUGA Masamitsu 東京工業高等専門学校, 電子工学科, 教授 (40123997)
AOKI Hiroyuki 東京工業高等専門学校, 電子工学科, 教授 (20249759)
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| Project Period (FY) |
2008 – 2010
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| Project Status |
Completed (Fiscal Year 2010)
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| Budget Amount *help |
¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2010: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2009: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2008: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
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| Keywords | 工学教育 / LSI設計技術教育 / LSI論理設計 / 論理回路設計教育 / ハードウェア設計記述 / Verilog-HDL / FPGA / ハードウエアー設計記述 / ハードウエア設計記述 |
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| Research Abstract |
HDL (Hardware Description Language) is essential for developing industrial LSI's. We have included an HDL logic circuit design laboratory in our experimental program for electronic engineering course students. Designed logic circuits by the students in HDL are configured on an FPGA (Field Programmable Gate Array) on the spot. The students have filled out questionnaires on HDL design experience. The paper reports our HDL logic circuit design laboratory, and tallies up the questionnaires.
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