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Study on Ultra-Low-Voltage Integrated Circuits for Self-Aligned Particle-Manipulation Technology

Research Project

Project/Area Number 20560324
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Electron device/Electronic equipment
Research InstitutionOsaka University

Principal Investigator

MATSUOKA Toshimasa  Osaka University, 工学研究科, 准教授 (80324820)

Project Period (FY) 2008 – 2010
Project Status Completed (Fiscal Year 2010)
Budget Amount *help
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2010: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2009: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2008: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Keywords集積回路 / 低消費電力 / 誘電泳動 / 自己整合 / センサ
Research Abstract

Sensor-On-CMOS with some sensors for comprehensive decision of situations and prevention of errors by redundancies has a limit in number of sensor types on the same chip in conventional production manners. Self-aligned particle-manipulation technique, which uses small-size quadruple electrodes for particle manipulation based on dielectrophoresis phenomenon and AC-wireless-powered small-size driver circuit for it, is studied, and its feasibility has been demonstrated.

Report

(4 results)
  • 2010 Annual Research Report   Final Research Report ( PDF )
  • 2009 Annual Research Report
  • 2008 Annual Research Report
  • Research Products

    (20 results)

All 2010 2009 2008 Other

All Journal Article (8 results) (of which Peer Reviewed: 6 results) Presentation (8 results) Remarks (4 results)

  • [Journal Article] A Design for Ultra-Low-Voltage CMOS Digital Circuits with Performance Characteristics Compensation2010

    • Author(s)
      王軍, 安江一紘, 松岡俊匡, 谷口研二
    • Journal Title

      Far East J.Electronics and Communications Vol.5, No.1

      Pages: 59-65

    • NAID

      120005611506

    • Related Report
      2010 Final Research Report
    • Peer Reviewed
  • [Journal Article] Low-Voltage Wireless Analog CMOS Circuits toward 0.5V Operation2010

    • Author(s)
      T.Matsuoka, J.Wang, T.Kihara, H.Ham, K.Taniguchi
    • Journal Title

      IEICE Trans. Fundamentals(招待論文) Vol.E93-A, No.2

      Pages: 356-366

    • NAID

      10026862981

    • Related Report
      2010 Final Research Report
  • [Journal Article] 超低電圧動作ディジタルCMOS 回路の特性補償に関する検討2010

    • Author(s)
      安江一紘, 王軍, 松岡俊匡, 谷口研二
    • Journal Title

      電子情報通信学会論文誌C Vol.J93-C, No.2

      Pages: 75-77

    • NAID

      110007538922

    • Related Report
      2010 Final Research Report
    • Peer Reviewed
  • [Journal Article] A Design for Ultra-Low-Voltage CMOS Digital Circuits with Performance Characteristics Compensation2010

    • Author(s)
      J.Wang, K.Yasue, T.Matsuoka, K.Taniguchi
    • Journal Title

      Far East J.Electronics and Communications

      Volume: Vol.5, No.1 Pages: 59-65

    • NAID

      120005611506

    • Related Report
      2010 Annual Research Report
    • Peer Reviewed
  • [Journal Article] 超低電圧動作ディジタルCMOS回路の特性補償に関する検討2010

    • Author(s)
      安江一紘, 王軍, 松岡俊匡, 谷口研二
    • Journal Title

      電子情報通信学会論文誌C J93-C

      Pages: 75-77

    • NAID

      110007538922

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Low-Voltage Wireless Analog CMOS Circuits toward 0.5V Operation2010

    • Author(s)
      T.Matsuoka, J.Wang, T.Kihara, H.Ham, K.Taniguchi
    • Journal Title

      IEICE Trans. Fundamentals E93-A

      Pages: 356-366

    • NAID

      10026862981

    • Related Report
      2009 Annual Research Report
  • [Journal Article] Design of A 0.5V Op-Amp Based on CMOS Inverter Using Floating Voltage Sources2008

    • Author(s)
      J.Wang, T.-Y.Lee, D.-G.Kim, T.Matsuoka, K.Taniguchi
    • Journal Title

      IEICE Trans.Electron Vol.E91-C, No.8

      Pages: 1375-1378

    • NAID

      10026819200

    • Related Report
      2010 Final Research Report
    • Peer Reviewed
  • [Journal Article] Design of A 0.5V Op-Amp Based on CMOS Inverter Using Floating Voltage Sources2008

    • Author(s)
      J. Wang, T. -Y. Lee, D. -G. Kim, T. Matsuoka, K. Tanlguchi
    • Journal Title

      IEICE Trans. Electron Vol. E91-C No. 8

      Pages: 1375-1378

    • NAID

      10026819200

    • Related Report
      2008 Annual Research Report
    • Peer Reviewed
  • [Presentation] 水中センサ用無線給電回路の検討2010

    • Author(s)
      宮脇祐介, 上田瞬, 松岡俊匡, 谷口研二
    • Organizer
      電子情報通信学会関西支部 第15回学生会研究発表講演会
    • Place of Presentation
      大阪大学
    • Year and Date
      2010-03-10
    • Related Report
      2010 Final Research Report
  • [Presentation] パルス駆動誘電泳動を用いた微粒子操作技術2010

    • Author(s)
      上田瞬, 宮脇祐介, 岡俊匡, 谷口研二
    • Organizer
      電子情報通信学会関西支部 第15回学生会研究発表講演会
    • Place of Presentation
      大阪大学
    • Year and Date
      2010-03-10
    • Related Report
      2010 Final Research Report
  • [Presentation] パルス駆動誘電泳動を用いた微粒子操作技術2010

    • Author(s)
      上田瞬, 宮脇祐介, 松岡俊匡, 谷口研二
    • Organizer
      電子情報通信学会 関西支部 学生会 第15回 学生会研究発表講演会
    • Place of Presentation
      大阪府吹田市
    • Year and Date
      2010-03-10
    • Related Report
      2009 Annual Research Report
  • [Presentation] 水中センサ用無線給電回路の検討2010

    • Author(s)
      宮脇祐介, 上田瞬, 松岡俊匡, 谷口研二
    • Organizer
      電子情報通信学会 関西支部 学生会 第15回 学生会研究発表講演会
    • Place of Presentation
      大阪府吹田市
    • Year and Date
      2010-03-10
    • Related Report
      2009 Annual Research Report
  • [Presentation] 超低電圧動作デジタルCMOS 回路の特性補償に関する検討2009

    • Author(s)
      安江一紘, 王軍, 松岡俊匡, 谷口研二
    • Organizer
      LSI とシステムのワークショップ2009
    • Place of Presentation
      北九州市
    • Related Report
      2010 Final Research Report
  • [Presentation] 超低電圧動作デジタルCMOS回路の特性補償に関する検討2009

    • Author(s)
      安江一紘, 王軍, 松岡俊匡, 谷口研二
    • Organizer
      LSIとシステムのワークショップ2009
    • Place of Presentation
      福岡県北九州市
    • Related Report
      2009 Annual Research Report
  • [Presentation] Study of Subthreshold-Operation CMOS Logic Circuit with Body-Bias-Control2008

    • Author(s)
      安江一紘, 王軍, 松岡俊匡, 谷口研二
    • Organizer
      IEEE International Meeting for Future of Electron Devices, Kansai(pp.95-96)
    • Place of Presentation
      Osaka, Japan
    • Related Report
      2010 Final Research Report
  • [Presentation] study of Subthreshold-Operation CMOS Logic Circuitwith Body-Bi as-Contro12008

    • Author(s)
      K. Yasue, J. Wang, T. Matsuoka, K. Taniguchi
    • Organizer
      IEEE International Meeting for Futureof Electron Devices, Kansai
    • Place of Presentation
      大阪
    • Related Report
      2008 Annual Research Report
  • [Remarks] ホームページ等

    • URL

      http://www.si.eei.eng.osaka-u.ac.jp/

    • Related Report
      2010 Final Research Report
  • [Remarks]

    • URL

      http://www.si.eei.eng.osaka-u.ac.jp/

    • Related Report
      2010 Annual Research Report
  • [Remarks]

    • URL

      http://www.si.eei.eng.osaka-u.ac.jp/

    • Related Report
      2009 Annual Research Report
  • [Remarks]

    • URL

      http://www6.eie.eng.osaka-u.ac.jp/

    • Related Report
      2008 Annual Research Report

URL: 

Published: 2008-04-01   Modified: 2016-04-21  

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