Impact of Network Reconfigurability on Parallel Computational Models.

• Project/Area Number: 20700014
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Fundamental theory of informatics
• Research Institution: Saga University
• Principal Investigator: MATSUMAE Susumu Saga University, 大学院・工学系研究科, 准教授 (60324828)
• Project Period (FY): 2008 – 2010
• Project Status: Completed (Fiscal Year 2010)
• Budget Amount: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000); Fiscal Year 2010: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000); Fiscal Year 2009: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000); Fiscal Year 2008: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
• Keywords: 並列アルゴリズム / プロセッサアレイ / メッシュ結合型並列計算機 / 再構成可能バス / 可能バス

Research Abstract

We study in those parallel computational models with dynamic reconfigurable network, especially in the reconfigurable mesh. We show that the reconfigurable mesh with N processors can work with O(log N) slowdown in time even if we deprive the mesh of its dynamic reconfigurable function.

Research Products

• [Journal Article] Effective Partitioning of Static Global Buses for Small Processor Arrays (2011)
  • Author(s): S.Matsumae
  • Journal Title: Journal of Information Processing Systems Vol.7, No.1 Pages: 85-92
  • Peer Reviewed
• [Journal Article] Impact of Reconfigurable Function on Meshes with Row/Column Buses (2011)
  • Author(s): S.Matsumae
  • Journal Title: International Journal of Networking and Computing (IJNC) vol.1, no.1 Pages: 36-48
  • NAID: 130005091730
  • Peer Reviewed
• [Journal Article] Impact of Reconfigurable Function on Meshes with Row/Column Buses (2011)
  • Author(s): Susumu Matsumae
  • Journal Title: International Journal of Networking and Computing (IJNC) Volume: Vol.1 Pages: 36-48
  • NAID: 130005091730
  • Peer Reviewed
• [Journal Article] Effective Partitioning of Static Global Buses for Small Processor Arrays (2011)
  • Author(s): Susumu Matsumae
  • Journal Title: Journal of Information Processing Systems Volume: Vol.7 Pages: 85-92
  • Peer Reviewed
• [Journal Article] Efficient Partitioning of Static Buses for Processor Arrays of Small Size (2010)
  • Author(s): S.Matsumae
  • Journal Title: Proc.of the 10th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP2010), Lecture Note in Computer Science (LNCS)
  • Peer Reviewed
• [Journal Article] Polylogarithmic Time Simulation of Reconfigurable Row/Column Buses by Static Buses (2010)
  • Author(s): S.Matsumae
  • Journal Title: Proc.of the 12th Workshop on Advances on Parallel and Distributed Processing Symposium (APDCM 2010)(in conjunction with the IEEE International Parallel & Distributed Processing Symposium(IPDPS2010))
  • Peer Reviewed
• [Journal Article] Efficient Partitioning of Static Buses for Processor Arrays of Small Size (2010)
  • Author(s): Susumu Matsumae
  • Journal Title: Proc.of the 10th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP2010), Lecture Note in Computer Science (LNCS), Springer
  • Peer Reviewed
• [Journal Article] Polylogarithmic Time Simulation of Reconfigurable Row/Column Buses by Static Buses (2010)
  • Author(s): Susumu Matsumae
  • Journal Title: Proc.of the 12th Workshop on Advances on Parallel and Distributed Processing Symposium (APDCM2010)
  • Peer Reviewed
• [Journal Article] Upper Bound on Cell Size for Hierarchical GAF (2009)
  • Author(s): Susumu Matsumae
  • Journal Title: Proc. of the 8th International Conference on Applications and Principles of Information Science (APIS2009) (CD-ROM)
  • Peer Reviewed
• [Journal Article] Impact of Reconfigurability on Meshes with Separable Row/Column Buses (2008)
  • Author(s): S.Matsumae
  • Journal Title: Proc.of the 2008 International Conference on Parallel and Distributed Processing Techniques and Applications (PDCCS2008)
  • Peer Reviewed
• [Journal Article] Improving Hierarchical Power Saving Technique with Location Information for Sensor Networks (2008)
  • Author(s): Susumu Matsumae
  • Journal Title: Proc. of the 2008 International Conference on Parallel and Distributed Processing Techniaues and Annlications (CD-ROM)
  • Peer Reviewed
• [Journal Article] Hier.archical. Low Power Consumption Technique with Location Information for Sensor Networks (2008)
  • Author(s): Susumu Matsumae
  • Journal Title: Proc. of the IASTED International Conference on Communication Systems and Networks (CSN 2008) (CD-ROM)
  • Peer Reviewed
• [Journal Article] Impact of Reconfigurability on Meshes with Separable Row/Column Buses? (2008)
  • Author(s): Susumu Matsumae
  • Journal Title: Proc. of the 2008 International Conference on Parallel and Distributed Processing Tee hniques and Applications (PDCCS 2008) (CD-ROM)
  • Peer Reviewed