A Research on Embedded Systems Suited for Energy Harvesting

• Project/Area Number: 20700049
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: Kyushu University
• Principal Investigator: ISHIHARA Tohru Kyushu University, システムLSI研究センター, 准教授 (30323471)
• Project Period (FY): 2008 – 2009
• Project Status: Completed (Fiscal Year 2009)
• Budget Amount: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000); Fiscal Year 2009: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000); Fiscal Year 2008: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
• Keywords: 計算機システム / 高信頼性 / 低消費電力 / 省エネルギー / 太陽電池

Research Abstract

This research seeks to create embedded computer systems running with renewable energy like solar energy. This research developed the following three items ; 1) a low power memory subsystem stably running with a low supply voltage around 0.5V, 2) a scalable processor which dynamically scales its performance and the power consumption, 3) a power estimation model which can analyze the energy consumption of application programs running on a cellar phone within an error of 10%.

Research Products

• [Journal Article] Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reduction (2009)
  • Author(s): S. Yamaguchi, Y. Ishitobi, T. Ishihara, H. Yasuura
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Vol.2 Pages: 189-199
  • Peer Reviewed
• [Journal Article] An Optimization Technique for Low-Energy Embedded Memory Systems (2009)
  • Author(s): T. Matsumura, T. Ishihara, H. Yasuu ra
  • Journal Title: IPSJ Transactions on System LSI D esign Methodology Vol.2 Pages: 239-249
  • NAID: 110009598039
  • Peer Reviewed
• [Journal Article] Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reduction (2009)
  • Author(s): S.Yamaguchi, Y.Ishitobi, T.Ishihara, H.Yasuura
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Vol.2 Pages: 189-199
  • Peer Reviewed
• [Journal Article] An Optimization Technique for Low-Energy Embedded Memory Systems (2009)
  • Author(s): T.Matsumura, T.Ishihara, H.Yasuura
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Vol.2 Pages: 239-249
  • NAID: 110009598039
  • Peer Reviewed
• [Presentation] A Run-Time Power Analysis Method using OS-Observable Parameters for Mobile Terminals (2010)
  • Author(s): Y.Kaneda, T.Okuhira, T.Ishihara, K.Hisazumi, T.Kamiyama, M.Katagiri
  • Organizer: International Conference on Embedded Systems and Intelligent Technology
  • Place of Presentation: タイチェンマイ
  • Year and Date: 2010-02-07
• [Presentation] Unification of Multiple Gated Flip-Flops for Saving the Power Consumption of Register Circuits (2010)
  • Author(s): T.Okuhira, T.Ishihara
  • Organizer: International Conference on Embedded Systems and Intelligent Technology
  • Place of Presentation: タイチェンマイ
  • Year and Date: 2010-02-06
• [Presentation] Unification of Multiple Gated Flip-Flops for Saving the Power Consumption of Register Circuits (2010)
  • Author(s): T. Okuhira, T. Ishihara
  • Organizer: Proc. of Int'l Conference on Embedded Systems and Intelligent Technology
• [Presentation] Real-Time Power Management for a Multi-Performance Processor (2009)
  • Author(s): T.Ishihara
  • Organizer: International SoC Design Conference
  • Place of Presentation: 韓国釜山
  • Year and Date: 2009-11-23
• [Presentation] ゲーテッドフリップフロップの多ビット統合によるレジスタ回路の低消費電力化 (2009)
  • Author(s): 奥平拓見、石原亨、井上弘士
  • Organizer: DAシンポジウム
  • Place of Presentation: 石川県加賀市
  • Year and Date: 2009-08-26
• [Presentation] Real-Time Dynamic Voltage Hopping on MPSoCs (2009)
  • Author(s): T.Ishihara
  • Organizer: International Forum on Embedded MPSoC and Multicore
  • Place of Presentation: 米国ジョージア州サバンナ
  • Year and Date: 2009-08-05
• [Presentation] ゲーテッドフリップフロップの多ビット統合によるレジスタの低電力化 (2009)
  • Author(s): 奥平拓見、石原亨、安浦寛人
  • Organizer: 電子情報通信学会総合大会
  • Place of Presentation: 愛媛県松山市(愛媛大学)
  • Year and Date: 2009-03-17
• [Presentation] OSから解析可能な無線通信端末の消費電力モデルとその生成手法 (2009)
  • Author(s): 石原亨、奥平拓見、久住憲嗣、神山剛、関根和寿、片桐雅二
  • Organizer: 情報処理学会システムLSI設計技術研究会
  • Place of Presentation: 新潟県佐渡市
  • Year and Date: 2009-03-05
• [Presentation] A Run-Time Power Analysis Method using OS-Observable Parameters for Mobile Terminals (2009)
  • Author(s): Y. Kaneda, T. Okuhira, T. Ishihara, K. Hisazumi, T. Kamiyama, M. Katagiri
  • Organizer: Proc. of International Conference on Embedded Systems and Intelligent Technology
• [Presentation] Real-Time Power Management for a Multi-Performance Processor (2009)
  • Author(s): T. Ishihara
  • Organizer: Proc. of Int'l SoC Design Conference
• [Presentation] ゲーテッドフリップフロップの多ビット結合によるレジスタ回路の低消費電力化 (2009)
  • Author(s): 奥平拓見, 石原亨, 井上弘士
  • Organizer: DAシンポジウム2009論文集
• [Presentation] [Invited Talk] Real-Time Dynamic Voltage Hopping on MPSoCs (2009)
  • Author(s): T. Ishihara
  • Organizer: International Forum on Embedded MPSoC and Multicore
• [Presentation] OSから解析可能な無線通信端末の消費電力モデルとその生成手法 (2009)
  • Author(s): 石原亨, 奥平拓見, 久住憲嗣, 神山剛, 関根和寿, 片桐雅二
  • Organizer: 情報処理学会研究報告
• [Presentation] ゲーテッドフリップフロップの多ビット結合によるレジスタの低電力化 (2009)
  • Author(s): 奥平拓見, 石原亨, 安浦寛人
  • Organizer: 電子情報通信学会総合大会
• [Presentation] A Single Cycle Accessible Two-Level Cache Architecture for R educing the Energy Consumption of Embedded Systems (2008)
  • Author(s): S. Yamaguchi, T. Ishihara, H. Y asuura
  • Organizer: International SoC Design Conference
  • Place of Presentation: 韓国・釜山
  • Year and Date: 2008-11-25
• [Presentation] A Single Cycle Accessible Two-Level Cache Architecture for Reducing the Energy Consumption of Embedded Systems (2008)
  • Author(s): S. Yamaguchi, T. Ishihara, H. Yasuura
  • Organizer: Proc. of Int'l SoC Design Conference