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Integrated Circuit for Low-Frequency Sensor Signal Processing with Natural-Energy Power Supply

Research Project

Project/Area Number 20760237
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeSingle-year Grants
Research Field Communication/Network engineering
Research InstitutionToyohashi University of Technology

Principal Investigator

WADA Kazuyuki  Toyohashi University of Technology, 工学部, 准教授 (00302943)

Project Period (FY) 2008 – 2009
Project Status Completed (Fiscal Year 2009)
Budget Amount *help
¥3,120,000 (Direct Cost: ¥2,400,000、Indirect Cost: ¥720,000)
Fiscal Year 2009: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2008: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Keywords低周波信号 / 低電圧 / 低電力 / 信号分割手法 / ADC / ディジタル基板雑音 / 生体信号処理 / 自然エネルギー / 逐次比較型 / ログドメイン
Research Abstract

An integrated circuit for low-frequency signal processing is developed to measure biological signals through wireless communication with portable equipments which are powered by energy source, the supply voltage of which is less than 1 V. First, filters for noise suppression, band limitation and baseband modulation are designed aiming at the point that the low-voltage and low-power filter structure which we have proposed is appropriate for baseband signal processing. A practical 0.6-V filter processing sensor signals is obtained even with 0.18-μm technology to achieve 89-dB dynamic range. Second, analog-to-digital converters (ADCs) following band limitation filters are considered. Successive approximation (SA),ΔΣ, and signal decomposition based pipeline types of architectures are investigated for low frequency and low voltage. Their noise performances are theoretically analyzed in detail and some techniques to enlarge signal-to-noise ratio by changing both wasteful structure are proposed. Last, digital substrate noise is coped with. Effectiveness with respect to a lot of noise sources are taken into account and a reliable simple model is introduced so that noise propagation in 3-D bulk is quantitatively discussed and 2 topologies effective for substrate noise suppression are derived. In conclusion, we are now sure that the aimed baseband signal processing is realizable with less than 0.8V.

Report

(3 results)
  • 2009 Annual Research Report   Final Research Report ( PDF )
  • 2008 Annual Research Report
  • Research Products

    (20 results)

All 2010 2009 2008

All Journal Article (6 results) (of which Peer Reviewed: 3 results) Presentation (14 results)

  • [Journal Article] 広範囲に分布するディジタル回路で発生する基板雑音の打消し回路2009

    • Author(s)
      鈴木寛人, 和田和千, 田所嘉昭
    • Journal Title

      信学論A Vol.J92-A,No.4

      Pages: 216-225

    • NAID

      110007384724

    • Related Report
      2009 Final Research Report
  • [Journal Article] 基板雑音を打ち消す信号を点状の領域へ注入する雑音低減回路2009

    • Author(s)
      鈴木寛人, 和田和千, 田所嘉昭
    • Journal Title

      電学論C Vol.129,No.8

      Pages: 1527-1533

    • NAID

      10025101660

    • Related Report
      2009 Final Research Report
  • [Journal Article] V Dynamic Biasing Filter With 89-dB Dynamic Range in 0. 18-μm CMOS2009

    • Author(s)
      Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro
    • Journal Title

      IEEE J. Solid-State Circuits Vol.44

      Pages: 2790-2799

    • Related Report
      2009 Final Research Report
  • [Journal Article] 基板雑音を打ち消す信号を点状の領域へ注入する雑音低減回路2009

    • Author(s)
      鈴木寛人, 和田和千, 田所嘉昭
    • Journal Title

      電気学会論文誌C 129

      Pages: 1527-1533

    • NAID

      10025101660

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-μm CMOS2009

    • Author(s)
      Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro
    • Journal Title

      IEEE Journal of Solid-State Circuits 44

      Pages: 2790-2799

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Journal Article] 広範囲に分布するディジタル回路で発生する基板雑音の打ち消し回路2009

    • Author(s)
      鈴木寛人, 和田和千, 田所嘉昭
    • Journal Title

      電子情報通信学会和文論文誌A Vol.J92-A

    • Related Report
      2008 Annual Research Report
    • Peer Reviewed
  • [Presentation] 電源電圧0.8Vで動作させる10bit逐次比較型ADCの試作回路における雑音の影響2010

    • Author(s)
      瀬川健太郎, 和田和千
    • Organizer
      電気学会・電子回路研究会
    • Place of Presentation
      群馬大学・同窓記念会館
    • Year and Date
      2010-03-26
    • Related Report
      2009 Annual Research Report
  • [Presentation] 電源電圧0. 8Vで動作させる10bit逐次比較型ADCの試作回路における雑音の影響2010

    • Author(s)
      瀬川健太郎, 和田和千
    • Organizer
      電気学会電子回路研究会
    • Related Report
      2009 Final Research Report
  • [Presentation] 微細プロセス向け高精度・低消費電力なパイプライン型ADCの構造2009

    • Author(s)
      中川雄介, 和田和千
    • Organizer
      電気学会・電子回路研究会
    • Place of Presentation
      宮崎・ホテルメリージュ
    • Year and Date
      2009-10-30
    • Related Report
      2009 Annual Research Report
  • [Presentation] 信号分割手法に基づくパイプライン型ADCの高精度化の検討2009

    • Author(s)
      中川雄介, 和田和千
    • Organizer
      電子情報通信学会ソサイエティ大会
    • Place of Presentation
      新潟大学・五十嵐キャンパス
    • Year and Date
      2009-09-18
    • Related Report
      2009 Annual Research Report
  • [Presentation] 比較器のオフセット電圧への耐性を高めた1.5bitパイプライン型ADC2009

    • Author(s)
      中川雄介, 和田和千
    • Organizer
      電気関係学会東海支部連合大会
    • Place of Presentation
      愛知工業大学
    • Year and Date
      2009-09-11
    • Related Report
      2009 Annual Research Report
  • [Presentation] MOSトランジスタを分割することで熱雑音を低減した増幅回路2009

    • Author(s)
      鈴木寛人, 和田和千, 田所嘉昭
    • Organizer
      電気学会電子回路研究会
    • Place of Presentation
      石垣市大濱信泉記念館
    • Year and Date
      2009-01-22
    • Related Report
      2008 Annual Research Report
  • [Presentation] 信号分割手法を適用したパイプライン型ADCの小容量構成2009

    • Author(s)
      中川雄介, 和田和千, 田所嘉昭
    • Organizer
      電気学会電子回路研究会
    • Place of Presentation
      石垣市大濱信泉記念館
    • Year and Date
      2009-01-21
    • Related Report
      2008 Annual Research Report
  • [Presentation] 信号分割手法を適用したパイプライン型ADCの小容量構成2009

    • Author(s)
      中川雄介, 和田和千, 田所嘉昭
    • Organizer
      電学電子回路研資
    • Related Report
      2009 Final Research Report
  • [Presentation] MOSトランジスタを分割することで熱雑音を低減した増幅回路2009

    • Author(s)
      鈴木寛人, 和田和千, 田所嘉昭
    • Organizer
      電学電子回路研資
    • Related Report
      2009 Final Research Report
  • [Presentation] 比較器のオフセット電圧への耐性を高めた1. 5bitパイプライン型ADC2009

    • Author(s)
      中川雄介, 和田和千
    • Organizer
      電気関係学会東海支部連合大会論文集
    • Related Report
      2009 Final Research Report
  • [Presentation] 信号分割手法に基づくパイプライン型ADCの高精度化の検討2009

    • Author(s)
      中川雄介, 和田和千
    • Organizer
      電子情報通信学会ソサイエティ大会論文集
    • Related Report
      2009 Final Research Report
  • [Presentation] 微細プロセス向け高精度・低消費電力なパイプライン型ADCの構造2009

    • Author(s)
      中川雄介, 和田和千
    • Organizer
      電学電子回路研資
    • Related Report
      2009 Final Research Report
  • [Presentation] Automatic tuning scheme for substrate noise cancellation circuit tolerant of large digital circuit2008

    • Author(s)
      H. Suzuki, K. Wada, Y. Tadokoro
    • Organizer
      Proc. 2008 IEEJ Analog VLSI Workshop
    • Related Report
      2009 Final Research Report
  • [Presentation] 2次ΔΣADCに対する利得可変積分回路の適用2008

    • Author(s)
      小山靖仁, 和田和千, 田所嘉昭
    • Organizer
      電学電子回路研資
    • Related Report
      2009 Final Research Report

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Published: 2008-04-01   Modified: 2016-04-21  

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