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Optimization algorithm for nonvolatile FPGA and its CAD tool implementation

Research Project

Project/Area Number 20K11725
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Review Section Basic Section 60040:Computer system-related
Research InstitutionThe University of Aizu

Principal Investigator

Daisuke Suzuki  会津大学, コンピュータ理工学部, 准教授 (00574675)

Project Period (FY) 2020-04-01 – 2023-03-31
Project Status Completed (Fiscal Year 2022)
Budget Amount *help
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2022: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2021: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2020: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Keywords半導体集積回路 / FPGA / 論理回路 / CAD / デジタル回路 / 電子回路 / 不揮発ロジック / 自動設計 / 回路設計 / 計算機アーキテクチャ / 配置配線 / CADツール
Outline of Research at the Start

Field-Programmable Gate Array (FPGA)は,種々のニーズに柔軟に対応可能なハードウェアとしてその重要性が高まっている。一方,揮発記憶をベースとする従来のFPGAでは待機電力の増加が深刻である。このような問題を根本的に解決するのが不揮発FPGAである。不揮発FPGAではデータを失うことなく高速に電源供給のオン/オフが可能であり,この特長を活用することで非稼働時の待機電力の削減が可能である。本研究では,「不揮発FPGA上にどのように効率的に所望の機能を実装するか」といった最適設計アルゴリズムならびにそのCADツール実装に取り組む。

Outline of Final Research Achievements

A field-programmable gate array (FPGA) is widely used in varieties of applications as owing to its flexible architecture. However, standby power which is consumed in the idle state to keep internal data has become a critical issue in the conventional FPGA. A nonvolatile FPGA where data is retained in a nonvolatile device with no power supply is one promising solution. In this research, optimization method of the hardware resource utilization and its CAD tool implementation, establishment of an environment for functional verification are performed for enhancing energy efficiency of the nonvolatile FPGA.

Academic Significance and Societal Importance of the Research Achievements

不揮発FPGAは従来のFPGAに代わる新たなハードウェア・プラットフォームとしてその研究開発が進められているが、単に記憶機能を不揮発に置き換えただけでは本来の性能は引き出せない。本研究はこのような観点から勧められたものであり、不揮発FPGA向けハードウェア資源の最適化、電源のオン/オフのスケジューリング手法、CADツール実装や機能検証のための環境構築などに関する知見は、新たなハードウェア設計論を切り拓くという意味で学術的意義を有する。またこれらの知見により不揮発FPGAの実用化が進むことで、高度な情報処理をより少ないエネルギー消費で実現できることが期待される。

Report

(4 results)
  • 2022 Annual Research Report   Final Research Report ( PDF )
  • 2021 Research-status Report
  • 2020 Research-status Report
  • Research Products

    (14 results)

All 2022 2021 2020 Other

All Journal Article (3 results) (of which Peer Reviewed: 2 results,  Open Access: 1 results) Presentation (10 results) (of which Int'l Joint Research: 9 results,  Invited: 3 results) Remarks (1 results)

  • [Journal Article] Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator2022

    • Author(s)
      SUZUKI Daisuke, OKA Takahiro、HANYU Takahiro
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 61 Issue: SC Pages: SC1083-SC1083

    • DOI

      10.35848/1347-4065/ac51bf

    • Related Report
      2021 Research-status Report
    • Peer Reviewed
  • [Journal Article] Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow2021

    • Author(s)
      SUZUKI Daisuke, HANYU Takahiro
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E104.D Issue: 8 Pages: 1111-1120

    • DOI

      10.1587/transinf.2020LOP0010

    • NAID

      130008070391

    • ISSN
      0916-8532, 1745-1361
    • Year and Date
      2021-08-01
    • Related Report
      2021 Research-status Report
  • [Journal Article] Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow2021

    • Author(s)
      Daisuke Suzuki and Takahiro Hanyu
    • Journal Title

      IEICE Trans. Information and Systems

      Volume: -

    • NAID

      130008070391

    • Related Report
      2020 Research-status Report
    • Peer Reviewed / Open Access
  • [Presentation] Design of a Low-Power FPGA-Based CNN Accelerator Based on Nonvolatile Logic-in-Memory Circuitry2022

    • Author(s)
      D. Suzuki, M. Natsui, A. Tamakoshi, Y. Takako, and T. Hanyu
    • Organizer
      2022 Int. Symp. Nonlinear Theory and Its Applications
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Spintronics-Based Nonvolatile FPGA and Its Application to Edge-AI Accelerator2022

    • Author(s)
      D. Suzuki and T. Hanyu
    • Organizer
      IEEE 15h Int. Symp. Embedded Multicore/Many-core Systems-n-Chip
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Spintronics-based Field-Programmable Gate Array-Its Overview and Application to Edge-AI Hardware2022

    • Author(s)
      D. Suzuki
    • Organizer
      Physics2022
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] Design of an Energy-Efficient Nonvolatile Lookup Table Circuit Using Active-Load-Localized Circuitry with Self-Terminated Writing/Reading2022

    • Author(s)
      D. Suzuki and T. Hanyu
    • Organizer
      2022 Int. Conf. Solid-State Devices and Materials
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] スピントロニクス素子ベース不揮発FPGA: 超低消費電力再構成可能ハードウェアプラットフォームへの挑戦2022

    • Author(s)
      鈴木 大輔, 夏井 雅典, 羽生貴弘
    • Organizer
      電子情報通信学会総合大会2022
    • Related Report
      2021 Research-status Report
    • Invited
  • [Presentation] Design of an Energy-Efficient Nonvolatile-FPGA-Based BCNN Accelerator Using an Active-Load-Localized Single-Ended Circuit Style2021

    • Author(s)
      SUZUKI Daisuke, OKA Takahiro、HANYU Takahiro
    • Organizer
      2021 Int. Conf. Solid-State Devices and Materials
    • Related Report
      2021 Research-status Report
    • Int'l Joint Research
  • [Presentation] Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once-Write Shifting2021

    • Author(s)
      SUZUKI Daisuke, OKA Takahiro、HANYU Takahiro
    • Organizer
      IEEE 14th Int. Symp. Embedded Multicore/Many-core Systems-n-Chip
    • Related Report
      2021 Research-status Report
    • Int'l Joint Research
  • [Presentation] MTJ-Based Nonvolatile FPGA: Circuit Technologies and Its Applications2021

    • Author(s)
      Daisuke Suzuki
    • Organizer
      Workshop on Computing with Unconventional Technologies
    • Related Report
      2021 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA2020

    • Author(s)
      Daisuke Suzuki and Takahiro Hanyu
    • Organizer
      ISMVL2020
    • Related Report
      2020 Research-status Report
    • Int'l Joint Research
  • [Presentation] Systematic Design Flow for Realizing MTJ-Based Nonvolatile FPGAs2020

    • Author(s)
      Yasuhiro Takako, Daisuke Suzuki, Masanori Natsui, and Takahiro Hanyu
    • Organizer
      SSDM2020
    • Related Report
      2020 Research-status Report
    • Int'l Joint Research
  • [Remarks] 会津大学 適応システム学講座 鈴木(大)研究室

    • URL

      https://u-aizu.ac.jp/~daisuke/

    • Related Report
      2021 Research-status Report

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Published: 2020-04-28   Modified: 2024-01-30  

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