| Budget Amount *help |
¥10,400,000 (Direct Cost: ¥8,000,000、Indirect Cost: ¥2,400,000)
Fiscal Year 2012: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Fiscal Year 2011: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
Fiscal Year 2010: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Fiscal Year 2009: ¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
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| Research Abstract |
In order to establish new design methodology that enable us to design and manufacture high-performance and high-reliable integrated circuits, a fast delay distribution estimation method that has enough accuracy was developed. Also, performance and performance improvement ratio of variable latency circuits in which delay error detection/correction mechanism is used were evaluated for various circuit, and a guideline to synthesize high-performance and high-reliable integrated circuits efficiently was obtained.
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