Evaluation of Low-Cost Circuit-level Techniques to Compensate Temporal Errors.

• Project/Area Number: 21300014
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Kyoto Institute of Technology
• Principal Investigator: KOBAYASHI Kazutoshi 京都工芸繊維大学, 工芸科学研究科, 教授 (70252476)
• Project Period (FY): 2009 – 2011
• Project Status: Completed (Fiscal Year 2011)
• Budget Amount: ¥9,490,000 (Direct Cost: ¥7,300,000、Indirect Cost: ¥2,190,000); Fiscal Year 2011: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000); Fiscal Year 2010: ¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000); Fiscal Year 2009: ¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
• Keywords: 一時故障 / VLSI / 信頼性

Research Abstract

We investigate the low-cost circuit technique to mitigate temporal soft errors caused by neutrons and alpha particles. We mainly focus on redundant flip-flops(FFs) and sensors to detect temporal errors. We developed a redundant FF called BCDMR which is 100x stronger than normal non-redundant FFs and also sensor circuit to detect multiple cell upsets(MCUs) to upset redundant FFs.

Research Products

• [Journal Article] An Area-efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets (2011)
  • Author(s): 山本, 濱中, 古田, 小林, 小野寺
  • Journal Title: IEEE Trans. on Nuclear Science Volume: vol.58 Issue: 6 Pages: 3053-3059
  • DOI: 10.1109/tns.2011.2169457
  • Peer Reviewed
• [Journal Article] Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures (2011)
  • Author(s): 濱中, 山本, 古田, 久保田, 小林, 小野寺
  • Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Volume: E94-A Issue: 12 Pages: 2669-2675
  • DOI: 10.1587/transfun.E94.A.2669
  • NAID: 10030533865
  • ISSN: 0916-8508, 1745-1337
  • Peer Reviewed
• [Journal Article] A 65 nm Complementary Metal-Oxide-Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit (2011)
  • Author(s): 松本, 牧野, 小林, 小野寺
  • Journal Title: Japanese Journal of Applied Physics Volume: vol.50 Issue: 4S Pages: 04DE06-04DE06
  • DOI: 10.1143/jjap.50.04de06
  • NAID: 210000070301
  • Peer Reviewed
• [Journal Article] An Area/Delay Efficient Dual-modular Flip-Flop with Higher SEU/SET Immunity (2010)
  • Author(s): J.Furuta, K.Kobayashi., et.al
  • Journal Title: IEICE Trans.Electron. E93-C Pages: 340-346
  • NAID: 10026824857
  • Peer Reviewed
• [Journal Article] Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells (2010)
  • Author(s): H.Sunagawa, H.Terada, A.Tsuchiya, K.Kobayashi, H.Onodera
  • Journal Title: IPSJ Trans.System LSI Design Methodology 3 Pages: 130-139
  • NAID: 130000251502
  • Peer Reviewed
• [Presentation] 微細化によるLSIの信頼性諸問題とその解決策 (2011)
  • Author(s): 小林和淑
  • Organizer: 広島大学先端物質科学研究科半導体集積科学専攻講演会
  • Place of Presentation: 東広島市(広島大学)(招待講演)
  • Year and Date: 2011-11-22
• [Presentation] Correlations between Well Potential and SEUs Measured by Well-Potential Perturbation Detectors in 65nm (2011)
  • Author(s): 古田, 山本, 小林, 小野寺
  • Organizer: Solid-State Circuits Conference
  • Place of Presentation: Jeju, Korea
  • Year and Date: 2011-11-16
• [Presentation] 微細化FPGAの信頼性諸問題 (2011)
  • Author(s): 小林和淑
  • Organizer: 関西FPGAカンファレンス
  • Place of Presentation: 大阪市(梅田センタービル)(招待講演)
  • Year and Date: 2011-10-28
• [Presentation] FPGA配線構造におけるRTNモデルを用いたNBTI遅延解析手法の検討 (2011)
  • Author(s): 籔内, 小林
  • Organizer: DAシンポジウム
  • Place of Presentation: 下呂
  • Year and Date: 2011-09-01
• [Presentation] 寄生バイポーラ効果を考慮したソフトエラーによる一過性パルスのモデル化と評価 (2011)
  • Author(s): 古田潤
  • Organizer: DAシンポジウム
  • Place of Presentation: 下呂温泉(水明館)
  • Year and Date: 2011-08-31
• [Presentation] FPGA配線構造におけるRTNモデルを用いたNBTI遅延解析手法の検討 (2011)
  • Author(s): 籔内美智太郎
  • Organizer: DAシンポジウム
  • Place of Presentation: 下呂温泉(水明館)
  • Year and Date: 2011-08-31
• [Presentation] スタンダードセルベースASICにおける多重化フリップフロップのソフトエラー耐性の評価 (2011)
  • Author(s): 増田政基
  • Organizer: スタンダードセルベースASICにおける多重化フリップフロップのソフトエラー耐性の評価
  • Place of Presentation: 兵庫県淡路市(淡路夢舞台)
  • Year and Date: 2011-08-01
• [Presentation] The Impact of RTN on Performance Fluctuation in CMOS Logic Circuits (2011)
  • Author(s): 伊東, 松本, 西澤, 砂川, 小林, 小野寺
  • Organizer: IEEE International Reliability Physics Symposium
  • Place of Presentation: Monterey, CA, USA
  • Year and Date: 2011-04-13
• [Presentation] Measurement of Neutron-induced SET Pulse Width Using Propagation-induced Pulse Shrinking (2011)
  • Author(s): 古田, 濱中, 小林, 小野寺
  • Organizer: IEEE International Reliability Physics Symposium
  • Place of Presentation: Monterey, CA, USA
  • Year and Date: 2011-04-13
• [Presentation] The Impact of RTN on Performance Fluctuation in CMOS Logic Circuits (2011)
  • Author(s): K.Ito
  • Organizer: IEEE International Reliability Physics Symposium
  • Place of Presentation: 米国カリフォルニア州モントレー(Hyatt Regency)
  • Year and Date: 2011-04-13
• [Presentation] Measurement of Neutron-induced SET Pulse Width Using Propagation-induced Pulse Shrinking (2011)
  • Author(s): J.Furuta
  • Organizer: IEEE International Reliability Physics Symposium
  • Place of Presentation: 米国カリフォルニア州モントレー(Hyatt Regency)
  • Year and Date: 2011-04-13
• [Presentation] Modeling of Random Telegraph Noise under Circuit Operation-Simulation and Measurement of RTN-induced delay fluctuation (2011)
  • Author(s): 伊東, 松本, 西澤, 砂川, 小林, 小野寺
  • Organizer: International Symposium on Quality Electronic Design
  • Place of Presentation: Santa Clala, CA, USA
  • Year and Date: 2011-03-15
• [Presentation] Modeling of Random Telegraph Noise under Circuit Operation-Simulation and Measurement of RTN-induced delay fluctuation (2011)
  • Author(s): K.Ito
  • Organizer: ISQED
  • Place of Presentation: Hyatt Regency, Santa Clala, CA, USA
  • Year and Date: 2011-03-15
• [Presentation] A 65nm Flip-Flop Array to Measure Soft Error Resiliency against High-Energy Neutron and Alpha Particles (2011)
  • Author(s): 古田, 濱中, 小林, 小野寺
  • Organizer: Asia and South Pacific Design Automation Conference
  • Place of Presentation: Yokohama, Japan
  • Year and Date: 2011-01-26
• [Presentation] A 65nm Flip-Flop Array to Measure Soft Error Resiliency against High-Energy Neutron and Alpha Particles (2011)
  • Author(s): J.Furuta
  • Organizer: ASP-DAC
  • Place of Presentation: Pacifico Yokohama, Yokohama, Japan
  • Year and Date: 2011-01-26
• [Presentation] Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations (2010)
  • Author(s): 籔内, 小林
  • Organizer: International Conference on Field Programmable Technologies
  • Place of Presentation: Beijing, China
  • Year and Date: 2010-12-09
• [Presentation] Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations (2010)
  • Author(s): M.Yabuuchi
  • Organizer: FPT
  • Place of Presentation: Tsinghua Univ, Beijing, China
  • Year and Date: 2010-12-09
• [Presentation] Circuit Performance Degradation on FPGAs Considering NBTI and Process Variations (2010)
  • Author(s): M.Yabuuchi
  • Organizer: SASIMI Workshop
  • Place of Presentation: Grand Formosa Regent, Taipei, Taiwan
  • Year and Date: 2010-10-18
• [Presentation] A 65nm CMOS 400ns Measurement Delay NBTI-Recovery Sensor by Minimum Assist Circuit (2010)
  • Author(s): 松本, 牧野, 小林, 小野寺
  • Organizer: International Conference on Solid State Devices and Materials
  • Place of Presentation: 東京
  • Year and Date: 2010-09-23
• [Presentation] A 65nm CMOS 400ns Measurement Delay NBTI-Recovery Sensor by Minimum Assist Circuit (2010)
  • Author(s): T.Matsumoto
  • Organizer: SSDM
  • Place of Presentation: Univ.of Tokyo, Tokyo, Japan
  • Year and Date: 2010-09-23
• [Presentation] A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element (2010)
  • Author(s): 古田, 濱中, 小林, 小野寺
  • Organizer: VLSI Circuits Symposium
  • Place of Presentation: Honolulu, Hawaii, USA
  • Year and Date: 2010-06-17
• [Presentation] A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element (2010)
  • Author(s): J.Furuta
  • Organizer: VLSI Circuit Symposium
  • Place of Presentation: Hilton Hotel, Honolulu, Hawaii, USA
  • Year and Date: 2010-06-17
• [Presentation] 基板バイポーラ効果によるSEUとMCUの発生機構の検討 (2010)
  • Author(s): 濱中力
  • Organizer: 電子情報通信学会技術研究報告 VLSI設計技術
  • Place of Presentation: 那覇市
  • Year and Date: 2010-03-10
• [Presentation] 遅延モニタ回路によるプロセス変動量の推定 (2009)
  • Author(s): Islam A.K.M.Mahfuzul
  • Organizer: DAシンポジウム2009
  • Place of Presentation: 石川県加賀市
  • Year and Date: 2009-08-27
• [Presentation] 高いSEU/SET耐性を持つ省面積・低遅延二重化フリップフロップ (2009)
  • Author(s): 古田潤
  • Organizer: 第22回回路とシステム軽井沢ワークショップ
  • Place of Presentation: 軽井沢
  • Year and Date: 2009-04-21
• [Remarks]
  • URL: http://www-vlsi.es.kit.ac.jp/globalwiki/wiki.cgi
• [Remarks]
  • URL: http://www-vlsi.es.kit.ac.jp/database/paper.php5
• [Remarks]
  • URL: http://www-vlsi.es.kit.ac.jp/database/paper.php5
• [Patent(Industrial Property Rights)] フリップフロップ回路 (2010)
  • Inventor(s): 古田潤、小林和淑、小野寺秀俊
  • Industrial Property Rights Holder: 京都工芸繊維大学
  • Filing Date: 2010-06-11
• [Patent(Industrial Property Rights)] フリップフロップ回路 (2010)
  • Inventor(s): 古田潤、小林和淑、小野寺秀俊
  • Industrial Property Rights Holder: 京都工芸繊維大学
  • Industrial Property Number: 2010-134066
  • Filing Date: 2010-06-11