Evaluation of Low-Cost Circuit-level Techniques to Compensate Temporal Errors.
Project/Area Number |
21300014
|
Research Category |
Grant-in-Aid for Scientific Research (B)
|
Allocation Type | Single-year Grants |
Section | 一般 |
Research Field |
Computer system/Network
|
Research Institution | Kyoto Institute of Technology |
Principal Investigator |
|
Project Period (FY) |
2009 – 2011
|
Project Status |
Completed (Fiscal Year 2011)
|
Budget Amount *help |
¥9,490,000 (Direct Cost: ¥7,300,000、Indirect Cost: ¥2,190,000)
Fiscal Year 2011: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Fiscal Year 2010: ¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000)
Fiscal Year 2009: ¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
|
Keywords | 一時故障 / VLSI / 信頼性 |
Research Abstract |
We investigate the low-cost circuit technique to mitigate temporal soft errors caused by neutrons and alpha particles. We mainly focus on redundant flip-flops(FFs) and sensors to detect temporal errors. We developed a redundant FF called BCDMR which is 100x stronger than normal non-redundant FFs and also sensor circuit to detect multiple cell upsets(MCUs) to upset redundant FFs.
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Report
(4 results)
Research Products
(35 results)