| Project/Area Number |
21360178
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Communication/Network engineering
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| Research Institution | University of Tsukuba |
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Principal Investigator |
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| Co-Investigator(Renkei-kenkyūsha) |
YAMAGUCHI Yoshiki 筑波大学, システム情報系, 講師 (30373377)
YOSHIHARA Ikuo 宮崎大学, 工学部, 教授 (20322315)
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| Project Period (FY) |
2009 – 2011
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| Project Status |
Completed (Fiscal Year 2011)
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| Budget Amount *help |
¥11,960,000 (Direct Cost: ¥9,200,000、Indirect Cost: ¥2,760,000)
Fiscal Year 2011: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2010: ¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2009: ¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
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| Keywords | 電子回路網 / 信号伝送 / 伝送 / 配線 / LSI / 集積 / ディジタル回路 / 信号品質 / シグナルインテグリティ / 遺伝的アルゴリズム / 集積回路 / シグナルインテグリテ |
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| Research Abstract |
Degradation of SI (Signal Integrity) is getting serious as frequencies of digital signals increase. In order to overcome this problem, we have proposed a novel technique based on the impedance mismatching. In this project, we have evaluated the new technique targeting digital signals at 30GHz operation frequency. As a result, we have shown that our technique can improve the distorted signals, which frequently happen in memory bus systems, better than the conventional techniques by 1.5 to 8 times.
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